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DE2-115 SDRAM without NIOS

Altera_Forum
Honored Contributor II
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I'm trying use the SDR SDRAM on the DE2-115 FPGA development board in verilog. I can't use NIOS as the interrupts aren't fast enough for my application.  

 

As far as I can tell I have 2 options: 

  1. Use the Qsys SDRAM component with an Avalon MM Master... or 

  2. Use the Altera SDR SDRAM controller from : http://www.altera.com/products/ip/altera/ocore_sdr_sdram.html 

 

 

Has anyone successfully implemented one of these solutions (or any other in verilog for the DE2-115 that doesn't use NIOS)? 

 

I've been ploughing away at it for a good couple of weeks and cannot get the SDRAM talking to the FPGA. Any help at all would be much appreciated. I've checked previous posts, but can't find any that have actually managed to get this working.
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Altera_Forum
Honored Contributor II
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What did you end up doing for this? 

 

I'm about to write my own SDRAM controller for the DE2-115 since I'm getting close to having a working async SRAM controller. 

 

I found this reference on line when I was doing some research a week or two ago: 

 

http://www.whoyouvotefor.info/altera_sdram.html 

 

Cheers, 

 

Doug
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Altera_Forum
Honored Contributor II
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Hi Doug, 

 

I ended up spending a long time reading through the SDRAM data sheet and writing a verilog SDRAM controller. It was a pain, but have now moved onto the SDCARD as well, which is an equal pain. Trial and error seem to be the way forward as the datasheets are slightly inaccurate. 

 

James
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Altera_Forum
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--- Quote Start ---  

Trial and error seem to be the way forward as the datasheets are slightly inaccurate. 

 

--- Quote End ---  

 

 

James, can you please share any particular issues that you worked around that might help others as they embark on building their own SDRAM controllers? Any hints or suggestions? Any particular methods you used PLLs or registers or IOBUFs or other FPGA chip features aside from raw HDL that helped? 

 

Thanks, 

 

Doug
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Altera_Forum
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A day late and a dollar short probably but for what it is worth, we routinely use the Altera SDRAM controller within Qsys and without a NIOS on our boards (not DE2-115). 

 

One example is a simple Qsys system with just the SDRAM controller and the "Avalon-MM Traffic Generator and BIST Engine" components, as a simple manufacturing diagnostic. 

 

I am not sure if there is something unique about the DE2-115 SDRAM which makes it difficult or not, but I did want to mention that in general it is easy to do option (1) in the original post. 

 

(i.e. it generally is not necessary to write your own SDRAM controller because the plain-text one from Altera works well, you can modify it if it's broken, and you don't need to use a NIOS). 

 

 

If you need to modify the Altera controller, or end up writing your own, one good resource (not for the chip on DE2-115, unfortunately) is the simulation models provided by Micron. 

In my case, we ended up using LPSDR and needed to modify the Altera SDRAM initialization sequence. Including the Micron model in the testbench was very helpful.
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Altera_Forum
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I used a single 133.33MHz PLL and raw HDL, that was it! 

To sum up what I did: 

 

To initialise: 

  • waited over 200µs for the SDRAM to boot up 

  • precharged all the banks 

  • auto-refreshed 8 times 

  • program the mode register (M0-4:0, M5:1, M6-8:0, M9:1) 

  • precharge all banks 

 

Then while idling just looped this: 

  • auto refresh 

  • nop & check for waiting read/write 

 

The problems I encountered were mainly around timing. The tRC, tMRD, latency etc times listed in the datasheet are not all correct. I can't remember exactly which ones were wrong, but some were and I had to go through a lot of trial and error to get it working.  

Basically I had to read 90% of the datasheet and then slightly wiggle some of the quoted numbers to get it working as expected.
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Altera_Forum
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Ted, 

 

Thanks for your thoughts. I want to write my own SDRAM controller not simply to have a working SDRAM controller, but to fully understand at a visceral, low level everything there is to know about using SDRAM and building a controller for it. 

 

It's very interesting you mentioned the Micron models because I have been looking around the Micron site for them. I just found them at the links below. 

 

The SDRAM in the DE2 is a a pair of ISSI IS42S16320D-7TL, in other words a 8M x 16 bits x 4 banks (512Mb) SDRAM with 7ns cycle time at CAS 3 or 7.5ns cycle time at CAS 2. Data sheet: http://www.issi.com/ww/pdf/42-45r-s_86400d-16320d-32160d.pdf 

 

This seems to be similar to one of these Micron part numbers: 

 

http://www.micron.com/parts/dram/sdram/mt48lc32m16a2tg-75-it?pc={428A5CC9-2A78-447E-939B-6F3A40D538C6} 

http://www.micron.com/parts/dram/sdram/mt48lc32m16a2tg-75?pc={428A5CC9-2A78-447E-939B-6F3A40D538C6} 

http://www.micron.com/parts/dram/sdram/mt48lc32m16a2p-75-l?pc={428A5CC9-2A78-447E-939B-6F3A40D538C6} 

http://www.micron.com/parts/dram/sdram/mt48lc32m16a2p-75-it?pc={428A5CC9-2A78-447E-939B-6F3A40D538C6} 

http://www.micron.com/parts/dram/sdram/mt48lc32m16a2p-75?pc={428A5CC9-2A78-447E-939B-6F3A40D538C6} 

 

However, they aren't remotely directly similar because Micron has no banks and does only CAS 3. I don't see any Micron SDR SDRAM newer than 2004. So, alas, these models aren't particularly useful for developing against the ISSI SDRAMs. :( Any other models you know about? 

 

From reading the ISSI SDRAM data sheet it seems CAS2 is good for things that do small random transfers all over the place and CAS3 is good for things that do large block transfers within the same segment. I'd probably implement the CAS2 initially since that seems more like my access pattern, and there really isn't much speed difference for this part anyway. (The faster parts do CAS3 cycle times much faster than CAS2.) 

 

It's a shame ISSI doesn't provide ModelSim (Verilog) models for these that I have found or their SRAM as used on the DE2-115 either (IS61WV102416BLL-10TLI). 

 

Thanks!
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