DE2-70 Verilog SDRAM Controller

[Altera_Forum]

Hi All, 

 Looking through the forums here I see that this question has been asked a lot, but I am struggling to actually find an answer to it.  I have a DE2-70 development kit (Cyclone II EP2C70 device) which has rwo ISSI IS42S16160B devices on it (32MB x2 SDRAM).  I would like to use these two SDRAM chips (actually 1 would be sufficent, but anyway) from my verilog custom logic. Understandably, I need an SDRAM controller and this is not something that I want to try implementing myself.  I have been scouring these forums and google for a couple of days now looking for a solution, but so far I am largely coming up empty.  I found the sdr sdram controller reference design (https://www.altera.com/support/software/download/refdesigns/sdram-controller/dnl-sdr-sram.jsp?swcode=www-ref-ssc-11-pc-vhdl) from Altera. However this seems to be for an older Cyclone development kit and is using a different SDRAM device. I am not sure if this would be a drop-in replacement or not (and if not, I have no idea how much would need to be modified to suit the devices I have available). Can anyone shed some light on to this?  I also found the 4-port SDRAM controller from one of the terasic examples (http://www.terasic.com.tw/attachment/archive/78/de2_lcm_ccd.zip). As of yet, I have not managed to find any documentation to accompany this though. Does anyone happen to know if any documentation exists for this?   Just to make it a little clearer. I do not want to use NiosII. I do not want to use Qsys. I do not want to use the SoPC builder. I want to avoid using the Avalon-MM (and Avalon-ST) interfaces if at all possible (this will be the only component in the entire system that would be using it).  Also, why does Altera not provide an SDR SDRAM IP MegaFunction core?  Best Regards Bidski

[Altera_Forum]

1) create a new (empty) Qsys project 

2) add the SDRAM Controller and configure it for your device organization and timing 3) connect the clock and reset 4) export the Avalon-MM Slave port and the Conduit for the SDRAM pins 5) generate the system 6) this is the end of using Qsys, forever 7) take the generated file (e.g. <qsys_project_name>/synthesis/submodules/sdram_0.v) and copy it wherever you like, modify it however you like, including removing the Avalon-MM should you care to.  It is a small hurdle to get your hands on what otherwise is a relatively straightforward piece of Verilog (crafted by a Perl script) with correct organization and timing for your devices.  Or, if you're OK with the GPL, check out the OpenCores project; but I'm not sure if that is more or less work as a starting point than the reference design you already found and are hesitant to use.