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Valued Contributor III
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DE5-NET JTAG Configuration Problem

Hi all, 

 

I tried to program the Stratix V FPGA on the DE5-NET board through the UBS Blaster cable. Each time, the programmer goes up to somewhere between 95% - 98% and fail. The error i get is "Error 209014 CONF_DONE pin failed to go high in device 1".  

I also noted that in the LED array near the USB blaster port on the board, only the JTAG Tx LED blinks while the programming is going on. 

 

Any ideas why this is happening and a way work around this is much appreciated? 

 

Isuru
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Valued Contributor III
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Re: DE5-NET JTAG Configuration Problem

The reason it fails at 99% is because the programmer does not have a way to check if the bitstream was OK until it has loaded it all into the FPGA, the check of CONF_DONE happens after all the data has been downloaded. 

 

So you're putting bad data into the FPGA and it's rejecting it. There are two possible reasons for this - either you somehow generated a bad sof/pof file or your data is getting corrupted on the way to the FPGA. 

 

Which sort of USB-Blaster are you using? The on-board one or one plugged into the 10 pin socket on the board?
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Valued Contributor III
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Re: DE5-NET JTAG Configuration Problem

Hi Wombat. I tried to download demo .sof files as well and got the same error. So it seems likely that the data is getting corrupted on the way as you said.  

 

I'm using the on-board USB blaster with the cable. I tried using different USB cables, just in case, but it didn't change anything. I also tried on different computers to see if it was a driver compatibility issue, but it was the same result each time.
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Valued Contributor III
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Re: DE5-NET JTAG Configuration Problem

You can turn down the USB-Blaster II JTAG clock speed with this command: 

 

jtagconfig --setparam <cable name> JtagClock <speed> 

 

The cable can't do every cable speed but it won't run faster than you specify, use --getparam to read the current value. 

 

The fastest three speeds it can run at 6M, 16M and 24M (the default).
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Valued Contributor III
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Re: DE5-NET JTAG Configuration Problem

I experienced an identical problem when I received a DE5-Net from a preproduction batch that uses an engineering sample (ES) FPGA. You can tell if you have one of these by removing the fan and seeing if the part number printed on the FPGA ends in ES. 

 

If it does, you will need to change the target device to 5SGXEA7N2F45C2ES in all projects, and recompile to demonstration projects if you want to use them. 

 

Also note that there is a serious bug in the flash programmer circuitry in Stratix V ES parts. If the flash programmer is used at all (e.g to load the demo bitstream when a board is powered on), then the FPGA goes into secure mode and won't accept any further programming commands (e.g from the USB blaster). To work around this Terasic have deliberately broken the flash programmer (so that it can't program the FPGA and hence it still accepts programming commands after power on) by incorrectly setting the MSEL dip switches near to the MAX II. If you have an ES FPGA then these will have to be set to DOWN-UP-UP-DOWN-UP-UP.
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