Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21615 Discussions

DM Pins on DDR2

Altera_Forum
Honored Contributor II
‎09-06-2010 10:35 PM
1,197 Views

Hello, 

 

I am trying to save some pins in interfacing to DDR2. I am thinking about grounding the DM pins on the memory module and not connecting the DM outputs from the DDR2 IP. In my implementation, I always write the full width of the bus, so the DDR2 IP should always be driving DM low. Is this a safe assumption? Are the DM pins used for anything other than write width? Is there something critical I am overlooking with this implementation? 

 

Thank you for you help.
0 Kudos

Link Copied

2 Replies
Altera_Forum
Honored Contributor II
‎09-07-2010 09:37 AM
459 Views

If you stick to whole-word writes you can safely forget about the DM pins and ground them at the DDR2 device(s). We have been doing that on all our projects sofar (for both SDR and DDR2 designs).

0 Kudos
Copy link
Altera_Forum
Honored Contributor II
‎09-07-2010 05:55 PM
459 Views

Thank you josyb. I will go with that then since it will save on pin count and routing.

0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.