Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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DRU implementation for SDI

Altera_Forum
Honored Contributor II
‎03-04-2013 11:48 AM
1,144 Views

Hi 

 

I am using cyclone IV FPGA to implement SD-SDI receiver with the gxb tranciver in 11x oversampling mode. Configuration I did is as follows : 

 

Reciever is configured for 2970 MHz : which is 11 times the the SD SDI data rate(270 MHz).  

 

Reciver is in lock to ref clock mode  

 

Reciver data width is set to 20 bit. 

 

Im looking for a Data Recovery Unit for this 11x oversampled data. Please help me ....................
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Altera_Forum
Honored Contributor II
‎03-12-2013 05:29 AM
419 Views

Hi all  

Any update on this.....
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