Hello,
I am seeing the below error in Quartus 12.0SP1 for my design;
Error (15361): DSP block input shift register starting with DATAA of mul_ln0_z_muladd_27_0__mac_mult1 must use same clock and clock enable signals File: CRYSTAL_CLL.vqm Line: 5676
Info (15362): DSP block multiplier node "mul_ln0_z_muladd_27_0__mac_mult1"
Info (15363): Register for port DATAA has clock signal clk_c
Info (15363): Register for port DATAA has clock enable signal delay_mux_dvalid_delay_1_ln2067_0_stage6_q_0
Info (15362): DSP block multiplier node "mul_z_muladd_27_0__mac_mult1"
Info (15363): Register for port DATAA has clock signal clk_c
Info (15363): Register for port DATAA has clock enable signal delay_mux_dvalid_delay_1_ln2067_0_stage7_q
I tried the message doc where it says;
CAUSE: The DSP block input shift register starting with the specified node contains registers that use different clock or clock enable signals. The registers in the input shift register must use the same clock and clock enable signals.
ACTION: Modify the configuration of the input shift register so that all registers use the same clock and clock enable signals or modify the input shift register to use logic cells outside the DSP block.
I did not understand much on this message.
Can someone help me out here to help understand the root cause for this error and how should i debug the same.
Regards,
freak
