Data I/O on FPGA

[Altera_Forum]

I am using a Stratix iii for my project (decoding files in a digita radio implementation) and need help (1)inputing data onto the board for processing, (2) sending the data back to a PC. 

 --> 1. Currently I am using a ROM file to grab my input, but it is inconvinent because my data files need to change, and that requires long recompilation just to get to use a new data file. Please suggest a quick and easy alternative, one that can seamless reading of my file, or better if it can read the data directly from the output of my matlab encoder. Please Please.   --> 2 I need a way of retriving the data for further processing in the PC, that can be simple enough to allow to access the data directly using C or Matlab code instead of having a file to open manually. But even that too will help,as long as it is better than my current method,using Signal Tap to retrieve the data. The problem is that this method cannot handle my average data samples (200K), and that even with the data I get I must open the file and scan it for the useful data before cutting it off for further processing. I would rather at the least the file was a fixed format where I can jst operate on it using my C code without need 2 cut any thing. Please Please Please, I am desperate.

[Altera_Forum]

The precise implementation strongly depends on the type of input/output you want to have and features of your design interfaces. 

Generally, I can recommend to use Nios II processor so you can easly send/receive data to your design running in the board via JTAG. You can use file operations (fopen, fclose, etc) to dump data to PC.

[Altera_Forum]

There is no really easy way to get data out of an FPGA to a computer. The signal tap works well for one time use. There is also a memory editor that works like signal tap, that allows you to read/write to memory in the FPGA thru JTAG. You have to select this option in the megafunction for the memory. The function is available under TOOLS. 

 When talking to the computer, my favorite way is the old serial port. Two pins on the FPGA with an RS-232 driver gives you easy access to the FPGA. You can use a simple terminal emulator to check that the port is working. I like termite (terminal emulator). The code for the UART is about a page each for tx/rx. OPENCORES has code for a UART, but they are usually fancier than you need. Also, MATLAB can talk directly to the port.  Second on the list would be USB. FTDI makes a parallel/serial to USB converter IC. They also provide the drivers for windows, so it looks like a serial port. You have to have a way to hook this up to your board, which may not be easy. Mouser sells demo boards and the chips. Again, you can use a terminal emulator to verify that it is working.   Third on my list would be Ethernet. If you are using the Stratix III demo board, there is an Ethernet port. If you look in the demo files for the board, I believe that there is a demo design on the CD for the ethernet port. I not a software person, nor do I much experience with NIOS, but I imagine that there is a learning curve with any choice you make.

[Altera_Forum]

thank u very much Uilka and Ronp. If I may just ask again, I am doing my project in VHDL meaning I am targeting the FPGA chips, is it possible for me to be using NIOS II and my VHDL in the same project? I figured programming the NIOS processor was user friendly but then I have long been doing everthing in VHDL and cant change now because I must finish the project in a week. I dont think I can use both.  

 Again I will go through what you have suggested quickly, hope I get to something fast.

[Altera_Forum]

You can use both in the same project. The SOPC project is compiled in a component that you can instantiate in your VHDL project.

[Altera_Forum]

Daixiwen thanx lots that is some useful info. I had made d wrong assumtion that the FPGA could use one at a time based on that it is programmed once (eg with VHDL), and when you program it again for NIOS it overwrites the first program. I guess I msut find me an example that combines SOPC and VHDL to get me up to speed. If you know some resources you can direct me to on the subject please do. 

 Thank you very much all once again. When I pass my Computer Eng. degree on 5 November 2009, I will come back again and thank you all.

[Altera_Forum]

A NIOS configuration is nothing more than a VHDL/Verilog project that includes a NIOS CPU. In fact you have two methods of combining a NIOS and custom VHDL code: 

- include a SOPC entity in your VHDL project, and add your VHDL code next to it - make a custom component in VHDL and connect it to the CPU inside SOPC builder. You can find an example here (http://www.altera.com/literature/hb/qts/qts_qii54007.pdf). It depends on what you want to do.