Data Transmission Using RJ45 Cable between dev board and laptop

[Altera_Forum]

Hi 

I'm totally a beginner and my question may seem a little bit stupid, but I would be grateful if you provide any help.  I want to transmit data between my laptop and a Stratix IV GX Development board using RJ45 cable but I don't really know what procedure I should follow. There are tons of reference designs/examples in Altera website (10Gb MAC, Triple-speed ethernet, lots of "application notes", etc.) and I'm completely confused.  I just want to transmit a single bit to the board, invert it and send it back to my laptop, so I don't really need any sophisticated hardware implemented in the board.  I'm familiar with Verilog and design flow using Quartus II software, but not really into communication protocols. It would much help if you provide me some procedure to follow to accomplish this task.  Thanks in advance, Behdad  P.S. I'm using Quartus II 13.1 64-bit on a linux machine.

[Altera_Forum]

You probably want to start here: 

http://www.altera.com/support/examples/nios2/exm-net-std-de.html  There really isn't any Verilog development work, it is all NIOS software.  Flipping your single bit and the need for "sophisticated hardware implemented in the board" is mostly because of the decision to use the RJ45 on the laptop as the other endpoint for communication: you need to at least match that level of sophistication in the board. (Ethernet MAC, PHY, and protocol processing either in NIOS software or HDL).

[Altera_Forum]

Thanks for your reply, I downloaded design files for my board, but ran into problems. (Actually I couldn't find any manual on how to use the design files, so I decided to figure it out myself) 

I tried to compile the project, but compilation failed. Then I tried to generate the Qsys files suspecting maybe those are not generated. The peripheral Qsys generated successfully, but the ethernet_system failed because the component "tse_mac" was not found.  Can you help me through using this example please?  Thanks

[Altera_Forum]

"eth_std_main_system.qsys" is the top level Qsys system that you need to open and generate. 

 Do that and then compile from Quartus.  It works fine in 12.1sp1

[Altera_Forum]

Must have forgotten to click the button, I have to type it again. 

I think the problem lies in my Quartus II version (which is 13.1) because when I open eth_std_main_system.qsys in Qsys, there's an error that component triple_speed_ethernet is not found, so it cannot be generated.  I'm wondering why there isn't a manual on how to use the design files. (Or maybe I couldn't find it.)