Info bout the timing analisys

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Info bout the timing analisys

869 Views

hello every body;

I didn't have a good knowledge bout Quartus and I have synthesized my design on it, and I want to know the following

1- How can I make the dynamic simulation on it.

2-where I found the maximum internal clk frequency for the registered operation.

3-what is the critical path.

thanks.

Link Copied

0 Replies

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.