Hello,
i want to debug my design which is fit into 4 altera fpgs(arria x) i.e., i have 4 different stp files.
Can any one help me in debugging my entire design using
only one trigger condition.
In signal tap ii analyzer, I know that multiple instances of same fpga can be managed using
trigger in and trigger out option.but how can i manage multiple fpga stp files (i want to debug entire design using only one trigger condition).
Can any one help me out here. Thanks in advance.
MJrao
