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Altera_Forum
Honored Contributor I
852 Views

Debugging the Hardware fault

I have Cyclone III fpga board with Ethernet interface and JTAG connector for Active Serial Programming through USB Blaster.  

 

If I plug in the Ethernet connector - the PC is not recognizing the hardware - i too can make the Ethernet connector light is not coming up. 

When i tried to load the boot-loader through USB Blaster - its not successful.  

 

Under this situation i am not able to guess what went wrong - is it the fpga or eeprom - Could any one can tell me other way to understand what i should look into to correctly figure out the issue 

 

-Suzane
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12 Replies
Altera_Forum
Honored Contributor I
32 Views

It sounds like you have a few problems and, maybe, don't understand how it should work. Is this a development board or a custom one? Can you add some schematics to the post? 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
32 Views

Hi Alex, I am not able to find the provision to include an attachment - could you please help to find the link

Altera_Forum
Honored Contributor I
32 Views

Click 'Go Advanced'. You can then add an attachment. 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
32 Views

Thanks, please find the attachment 

 

Suzane
Altera_Forum
Honored Contributor I
32 Views

1) Can you program the FPGA directly via your JTAG connector? - P1. 

 

2) Will the FPGA configure from your serial PROM? - U1. 

 

3) The FPGA looks to be connected up correctly. Are your power rails good - at the right levels? Are they noisy? (Perhaps not given how you generate them). 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
32 Views

The Power rails are just perfect - No, from the JTAG Connector I am not able to program - i am using usb blaster - its unsuccessful. How do i know whether i have fried the FPGA. But these are extreme circumstances because the board has been working and after a long time when i started testing - i found its not responding. 

Could you confirm me certain things : if a bootloader program is loaded - where exactly it resides - FPGA OR eprom. A bunch of 7-8 status LEDS on board which earlier during power quite a# of leds used to blink in different timing cycle almost with 1 and 2 seconds. At this moment only one led blinks 1/second and rest of the leds remains off
Altera_Forum
Honored Contributor I
32 Views

I'm a little confused. You say you cannot program the FPGA via JTAG. However, "1 LED blinks". Is it one of D10-D19? If so the FPGA is clearly doing something. Or is it another LED? Which LED is blinking? 

 

If your power rails are all good but you can't program the FPGA via JTAG, then it doesn't look good for your FPGA - especially if the board was previously working. You should always be able to reprogram the FPGA via JTAG. 

 

You won't be the first to fry your FPGA without knowing why. I see you've put quite a bit of protection into your design. Are you being careful with your handling of your board? 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
32 Views

Yes, one LED blink D18. Yes, very much i am particular in handling my boards all . When i power up the board one LED D18 blinks at a lower rate may be one blink per 2 second

Altera_Forum
Honored Contributor I
32 Views

The board is not recognizing the ethernet port also when connected to a pc also. I am ruling out the possibility of USB BLASTER non functional

Altera_Forum
Honored Contributor I
32 Views

USB Blaster is being recognized by the PC - so there must be something wrong - is eeprom could be an issue

Altera_Forum
Honored Contributor I
32 Views

If that LED is blinking then the FPGA must be configuring from the serial PROM/EEPROM U1. So, no. I don't think you have a problem with your EEPROM. 

 

The fact you can't talk to the FPGA via JTAG is worrying. I've never known a 'working' board (that boots from it's EEPROM) not respond via JTAG. 

 

 

--- Quote Start ---  

The board is not recognizing the ethernet port also when connected to a pc also 

--- Quote End ---  

 

What makes you think this? No LINK? Is the Phy (U13) getting the right clocks? Is it out of reset (RESET_N)? 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
32 Views

Hi Alex, 

I did not check the clocks. I am trying to go by some common sense - what i am trying to mean - what could be common thing involved which has disrupted the communication between JTAG to FPGA and PHY to FPGA ? AT LEAST I AM NOT ABLE TO FIGURE OUT 

 

Regards 

Suzane