Decimation or re-sampling filter

[Altera_Forum]

For a software defined radio, we need to resample down factor 1000x. Specifically, we are bringing in a signal at 20 MSps and then decimating down in real-time to 20 KSps [for processing gain]. How do I figure out what size/type FPGA I need to accomplish this task? Our need is to accomplish this for a high-volume, consumer electronics product [i.e. low priced FPGA]. 

 Any advice is welcome.  Thanks,  Rob Higher Ground LLC

[Altera_Forum]

Look at the CIC Users Guide. With such a high decimation ratio, you'd probably: 

 1) Multiply with an NCO signal to mix the signal to baseband  2) Run the complex-valued baseband signal through a decimating CIC filter  3) Run the CIC output through a band-shape correction filter, possibly a half-band filter with decimate by 2.  Its impossible to figure out the resources, without also knowing the dynamic range requirements of your application, i.e., how many bits you need and the out-of-band rejection you need from your filters. You pretty much have design the filters, place-and-route, and then decide whether to select an appropriate sized FPGA, or to further optimize to reduce the logic usage.  The handbooks for the IP have some resource estimates. You could start with that, and then create a few designs using Quartus.  Your initial sample rate is quite slow, and your over-sampling ratio is high. I suspect you'll have no issue using the Cyclone series devices.  Start with a large Cyclone IV, and then work your way to the cheaper devices. The cheaper you go, the fewer features you have, eg., less feature-full DSP blocks. You'll have to 'play' with a few designs to see what works for your application.  Note that there are probably ASICs that already do what you want - TI comes to mind. Before deciding that an FPGA is your low-cost solution, check the competition. You might find that a MAX II + SDR ASIC is the lowest cost.  Cheers, Dave

[Altera_Forum]

Dave, 

 Thank you! We will be using 12 bits.  I have been looking for an ASIC solution. Can you suggest some specific parts that I should research?  Rob

[Altera_Forum]

Search for digital downconverter. 

 http://www.ti.com/lsds/ti/analog/rfif.page http://www.ti.com/lit/ds/symlink/gc5316.pdf http://www.ti.com/lit/ds/symlink/gc5018.pdf  http://www.analog.com/en/digital-to-analog-converters/digital-updown-converters/products/index.html http://www.analog.com/static/imported-files/data_sheets/ad6636.pdf  Even if you do decide to go for an FPGA solution, these data sheets tell you what DSP blocks/steps you need in the FPGA.  Another useful link that showed up in the Google search:  http://rfdesign.com/mag/605rfdf3.pdf  Cheers, Dave

[Altera_Forum]

CIC decimators have low resource requirements but a rather smooth filter function in frequency domain. They have been extensively used for SD ADC and are still in recent designs. If a more rectangular frequency domain window is required, e.g. for audio applications, at least the last decimator stage must use a different filter topology or at least a correction filter, as already mentioned.  

 A detailed discussion of CIC decimators and combinations with other types can be e.g. found in Meyer-Baese dsp with fpga.  Regards, Frank