Decoupling for C-IV GX

[Altera_Forum]

Hi, 

 I am using EP4CGX150CF23. I am not conversant with the PDN tool. I have very little idea of decoupling and bypassing.   I came across the decoupling schematics for EP4CGX150DF31. There X2Y caps are being used. The decoupling caps required for individual power pins is not shown. I want to know what is the recommendation for individual power pins.   Any help will be highly appreciated.  thanks and regards, rajesh

[Altera_Forum]

Actually the recommendation for BGAs is not to decouple on each power pin but to decouple the planes instead. Connect each power pin to the relevant power plane with their own via, and connect each decoupling capacitor to the relevant plane with its own via (or, if you have the space, with multiple vias for each capacitor). This is the best way to reduce the series inductance between the BGA and the decoupling capacitors.

[Altera_Forum]

--- Quote Start ---  Actually the recommendation for BGAs is not to decouple on each power pin but to decouple the planes instead. Connect each power pin to the relevant power plane with their own via, and connect each decoupling capacitor to the relevant plane with its own via (or, if you have the space, with multiple vias for each capacitor). This is the best way to reduce the series inductance between the BGA and the decoupling capacitors.  --- Quote End ---   Do You suggest a dedicated whole power planes for each voltage or a single power plane consisting of several islands for each voltage?

[Altera_Forum]

Both are possible. Just be careful about the placement of your decoupling capacitors to reduce the high frequency supply and return current loops as much as possible. Generally I'm using a dedicated power plane for VCCINT, two other power planes with islands for the different VCCIO, VCCD_PLL and VCCA, and at least 3 ground planes. But this depends highly on your board routing and how many voltages you need to provide to the FPGA.