Delay Fault test on 74 series chips problem encountered

[Altera_Forum]

Hi! 

 I am now doing a project on delay fault test on 74series chips. The attachment is my quartus II project with design for delay fault test on 7400 (two inputs Nand gates) as example.  Since the chips delays are in nanoseconds, I use pll in quartus to step up the frequency from 50Mhz to 500Mhz and I connected to the 74161 ( BCD counter).  I am using Altera DE2 board for my delay fault test on HD74LS00P chip. From the data sheet, it say that this chip has at least 9 to 15 ns switching characteristic. But when I use my quartus design on the hardware, my 74161 counter is not functioning at all. May I know why and how to solve it? Does the high frequency inputs can test on the hardware like 74 series IC chips?  Thanks!

[Altera_Forum]

Cyclone II doesn't specify an explicite maximum core clock frequency, but numbers above 400 MHz won't leave much margin for logic between register. Set up at least a classical timing analyzer for your design, specifying the 50 MHz input clock, and see the 4-Bit counter (74161) failing setup time by 0.82 ns. In other words, it can run at 350 MHz maximum. There may be more issues with yet unconstrained external signals, however, the simple test shows, that you have to run the design at lower speed or reduce the fast part to more basic operations. The probably best solution is to read the pattern from DUT by a DDR register clocked at 400 MHz, giving you 1.25 ns timing resolution.