Delay in Pulses and Oscilloscope as simulator

[Altera_Forum]

Hi everyone, 

Could you please guide me regarding the following problem. I have learnt to write a code for providing delay for output signal. but I need to see the delay in the Oscilloscope. I did the simulation in the modelsim and it is OK. let me show you the ports of my design.  entity delay is  port( Clk : in std_logic; valid_data : in std_logic; -- goes high when the input is valid. data_in : in std_logic; -- the data input data_out : out std_logic --the delayed input data. ); end delay;  As you know in the modelsim we can see the input and output waveform at the same time. Is it possible to do same in the Oscilloscope? I mean, seeing the inputs and outputs waveforms at the same time and observe the delay.  Thank you in advance for your assist.

[Altera_Forum]

If you want to see the same sorts of signals as you do in Modelsim, then you should try using SignalTap II in your hardware. 

 1. In Quartus, select Tools->SignalTap II Logic Analyzer.  2. The GUI will start with the "Setup" tab shown. Double click in the area that says "Double-click to add nodes"  3. In the Filter menu, select SignalTap II: Design Entry (all names), and then click on the List button.  4. Double click on the nodes you want to probe - they'll move to the right-side of the GUI. Click Ok.  5. Click the '...' button next to the "Clock" on the right-side of the main GUI. Select the clock signal.  6. Select a sample depth of 1K  7. Save the SignalTap II instance, and select OK when it asks if you should add it to the project.  8. Re-synthesize the design.  9. Download the design  10. Start SignalTap II and it will detect the instance in your design.  11. Set a trigger condition and capture a trace.   The trace should look like the Modelsim plots.  I just typed the above in from memory, so I've likely missed a couple of steps. The Quartus Handbook has a pretty good description of the process.  Cheers, Dave