Design decision about OpenRISC and SDRAM clocks.

[anm]

Hi,

I am implementing a custom design on a DE0-CV board, of an OpenRISC processor. I want to connect the OpenRISC Processor to an onboard SDRAM.

The SDRAM has its own controller. This controller has two 2 clocks, one operating on the frequency of the SDRAM and one operating on the frequency of the Bus that is connected on (Wishbone Bus). The Wishbone Bus operates on the same frequency as the OpenRISC.

I have a general design question about this. What is it most preferable:

a) The SDRAM, SDRAM controller and OpenRISC to operate on the same frequency?

b) The SDRAM and SDRAM controller to operate on a frequency higher than that of the OpenRISC processor?

c) The SDRAM and SDRAM controller to operate on a frequency lower than that of the OpenRISC processor?

Any guidelines, opinions or references are welcome!

Thank you in advance for your responses.

Kind regards,

anm

[AnilErinch_A_Intel]

Hi 

It looks like you are looking for an answer to the question like whether over clocking the RAM over CPU is advisable. 

Which is heavily dependent on what kind of application you want to build. 

Also if you are able to achieve the timing closure , there are no limitations to  different frequencies being used in different buses. 

Thanks and Regards

Anil