Difference between CML and High Speed Differential IO transceiver I/O standard

[FRoth]

We are using A10 transceiver blocks and we use CML and High Speed Differential I/O pin standards interchangeably, since these two standards seem to us to basically describe the same thing. Could you please explain the differences between CML and High Speed Differential I/O, so we could confirm our approach?

Thank you for Your help

[CheePin_C_Intel]

Hi FRoth,

Yes your understanding is correct. In term of the A10 XCVR, when you use CML and High Speed Differential I/O, the TX and RX specs are actually the same. The only difference is that the A10 TX only support High Speed Differential I/O standard but RX can support High Speed Differential I/O, CML , Differential LVPECL , and LVDS standards.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

[CheePin_C_Intel]

​For further details on the A10 TX and RX specs, you may also refer to the Receiver Specifications and Transmitter Specifications tables in the A10 datasheet. Thank you.