Different outputs with different delays

[Altera_Forum]

Hi every, 

 I am using this code for providing 20 clock cycle delay in the output. the process is when the valid data become 1, the counters start counting and after 20 clock cycle the output will be valid data. I have simulated also in Modelsim and it works nice. the problem is I have only 1 output, but i need more out put with different clock cycle delays. for example if the first output has 20 cycle delay, the second has to be 30 cycle and the third has to be be 40.  This is the code with 1 output:  library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all;   entity delay is  port( Clk : in std_logic;  valid_data : in std_logic; -- goes high when the input is valid.  data_in : in std_logic; -- the data input  data_out: out std_logic --the delayed input data.  ); end delay;   architecture Behaviora of delay is   signal c : integer := 0; constant a : integer := 20; --number of clock cycles by which input should be delayed. signal data_temp : std_logic :='0'; type state_type is (idle,delay_c); --defintion of state machine type signal next_s : state_type; --declare the state machine signal.   begin   process(Clk) begin  if(rising_edge(Clk)) then  case next_s is   when idle =>  if(valid_data= '1') then  next_s <= delay_c;  data_temp <= data_in; --register the input data.  c <= 1;  end if;  when delay_c =>  if(c = a) then  c <= 0; --reset the count  data_out <= data_temp; --assign the output  next_s <= idle; --go back to idle state and wait for another valid data.  else  c <= c + 1;  end if;  when others =>  NULL;  end case;  end if; end process;      end Behaviora; ------------------------------ and the testbench is:  LIBRARY ieee; USE ieee.std_logic_1164.ALL;   ENTITY tb IS END tb;   ARCHITECTURE behavior OF tb IS     signal Clk : std_logic := '0';  signal valid_data : std_logic := '0';  signal data_in, data_out : std_logic := '0';  constant Clk_period : time := 20 ns;   BEGIN    -- Instantiate the Unit Under Test (UUT)  uut: entity work.delay PORT MAP (  Clk => Clk,  valid_data => valid_data,  data_in => data_in,  data_out => data_out  );    -- Clock process definitions  Clk_process :process  begin  Clk <= '0';  wait for Clk_period/2;  Clk <= '1';  wait for Clk_period/2;  end process;  -- Stimulus process  stim_proc: process  begin  wait for 40 ns;   valid_data <= '1';  data_in <= '1';  wait;  end process;   END;   --------- As I said it works fine but I need three outputs and with 20, 30 and 40 cycles delays. I did something like this but it doesn't work on the modelsim. I don't know where I am wrong in the code or in the testbench.  The code I made is like this: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all;   entity delay is  port( Clk : in std_logic;  valid_data : in std_logic; -- goes high when the input is valid.  data_in : in std_logic; -- the data input  data_out_a : out std_logic; --the delayed input data.  data_out_b : out std_logic; --the delayed input data.  data_out_e : out std_logic --the delayed input data.  ); end delay;   architecture Behaviora of delay is   signal c : integer := 0; constant a : integer := 20; --number of clock cycles by which input should be delayed. constant b : integer := 30; --number of clock cycles by which input should be delayed. constant e : integer := 40; --number of clock cycles by which input should be delayed. signal data_temp : std_logic :='0'; type state_type is (idle,delay_c); --defintion of state machine type signal next_s : state_type; --declare the state machine signal.   begin   process(Clk) begin  if(rising_edge(Clk)) then  case next_s is   when idle =>  if(valid_data= '1') then  next_s <= delay_c;  data_temp <= data_in; --register the input data.  c <= 1;  end if;  when delay_c =>  if(c = a) then  data_out_a <= data_temp;  if(c = b) then  data_out_b <= data_temp;  if (c = e) then  c <= 1; --reset the count  data_out_e <= data_temp; --assign the output  next_s <= idle; --go back to idle state and wait for another valid data.  else  c <= c + 1;  end if;  end if;  end if;   when others =>  NULL;  end case;  end if; end process;      end Behaviora;    Thank you everyone for help. I have to mention I am new in VHDL.

[Altera_Forum]

You have misplaced 'end if ' lines and the c <= c + 1 statement never executes.

[Altera_Forum]

Thank you Cris, 

 Could you please be more specific. Where am I wrong?

[Altera_Forum]

According to your code, C only increments when C = 20 (which will never happen). I think you need to re-asses the code.

[Altera_Forum]

I did it.  

Thank you both.