Digital input slew rate or rise time, fall time requirements for 10M16SCU169I7G

[NBK]

Hello,

Does 10M16SCU169I7G FPGA has any constraints for DIgital input slew rate or maximum allowed rise/fall times. if yes, what are the maximum allowed limits?

Thanking you in advance.

[FvM]

I don't see explicite specification in datasheet. If you have input signals with slow edges, consider to enable schmitt-trigger feature for respective inputs.

[NBK]

Thank you very much for the reply.

[TingJiangT_Intel]

If further more problem on this please let us know

[TingJiangT_Intel]

 I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.