DisplayPort MST Failure

[AdamKao]

Hi Deshi,

The design works fine outputting DisplayPort video in MST mode and the stream count is set to 2 at 1920x1080p @ 60Hz output, but it only works on one channel when the refresh rate is increased to 120Hz.(297MHz pixel clock)

I have lowered frequency to 277272(277.272MHz) but the result is the same.

Thanks.

Adam

[BoonT_Intel]

Hello Adam,

May I know what is the FPGA device?

[AdamKao]

Cyclone 10 GX

Thank you.

Adam

[Deshi_Intel]

Hi Adam,

I have taken over this case back

It's good to finally able to communicate with you directly without going through the dFAE. 

There are few questions that I would like to clarify with you.

1. All the while we are taking about Arria V FPGA, your design files that DFAE shared with me earlier is also Arria V. Just curious why you suddenly mention about Cyclone 10 GX FPGA ? Can you clarify again which FPGA that you are using in your project development ?

Below is also some follow up questions from my previous enquiry that I didn't hear back from you yet.

1. You shared with us 2 MSA log file before (MSA_SST.txt and MSA_MST.txt)
   • SST naming is confusing as I still can see 2 stream result in the MSA log. 
   • Can you clarify is this just file naming error ? Where both are actually MST design MSA log ?
   • Something like MSA_SST.txt = MST@60Hz,  MSA_MST.txt = MST@120Hz ?
2.  Have you reviewed you MST stream 0 and stream 1 design to ensure there is no design difference particularly on the clocking side ?
3. Also does your MST design meet Quartus Timequest design timing closure with positive margin slack ? Is your stream clock frequency correct ?
4. Do you have a chance to try other refresh rate between 60Hz to 120Hz to see if it works ? Like eg : 75Hz ?
5. For the btc_dptxll_stream_set_pixel_rate = 297000. It's meant for 2200 x 1125 x 120Hz. 277272 setting is meant for lower refresh rate. Just to confirm you are not running 120Hz refresh rate with 277272, right ?
6. From the earlier MSA log, I can see DisplayPort link training failed and DP data rate reduced from 5.4G to 2.7G. Do you have DP Aux transaction decoder equipment like Unigraf DPA-400 to decode Aux log transaction to help us understand and isolate what's the issue with the "bad DisplayPort link training process"
   •       https://www.unigraf.fi/product/dpa-400-displayport-aux-channel-monitor/?gclid=CjwKCAjwsan5BRAOEiwALzomX1UC4-QrnYbNJDVv4z47HBi2N7aSHw_ux4uLjwZZZlCz5b-R6O56PxoCfmkQAvD_BwE

Thanks.    

Regards,

Deshi

[AdamKao]

Hi Deshi,

Yes you are right we are talking about Arria V FPGA and I am using the Arria V for the DP MST project. Sorry I was confusing you. Because there are several projects are going and one of the project is using the Cyclone 10 but NOT for this project that we are discussing. I have answers for your questions below:

1. Regarding the MSA log file (MSA_SST.txt and MSA_MST.txt) I shared, both of them are the same hardware and the same FPGA design. The difference is :

MSA_SST.txt = connecting output to a SST monitor.

MSA_MST.txt = connecting output to a MST monitor.

2. Ensure MST stream 0 and stream 1 design are the same. I create a simple pattern generator in the design and then connect to the two input of DP IP. That is to say two input of DP IP for two stream are fully identical.
3. MST design meets Quartus Timequest design timing? Yes, but in fact there is a unconstrained clock is reported as below:

gxb_tx:gxb_tx_i|altera_xcvr_native_av:gxb_tx_inst|av_xcvr_native:gen_native_inst.av_xcvr_native_insts[0].gen_bonded_group_native.av_xcvr_native_inst|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts[0].av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_OUT
I don’t how to fix it due to it is a signal deep inside the DP IP.

4. Do you have a chance to try other refresh rate between 60Hz to 120Hz to see if it works ? Like eg : 75Hz ? I have try to lower the clock rate to 277.272MHz so the refresh rate changes to 112Hz. The result is the same.

5. Question 5, please refer to question 4.

6. I don’t have DP Aux transaction decoder equipment. Is there other way to do the debug in command shell?

. 

Regards,

Adam

[Deshi_Intel]

Hi Adam,

Sorry for the late respond as I miss out your feedback in early Aug.

Thanks for the clarification on SST vs MST log is due to different monitor.

• In this case, I would categorize them as different hardware setup as the transceiver channel performance on SST monitor maybe difference than MST monitor

Is your MST monitor = Asus PQ321Q ?

• One thing that I want to clarify with you is you are not using typical MST test setup where we are either using MST hub or MST daisy chain monitor
• So, I am not sure exactly how your MST monitor works
• Would you be able to perform MST daisy chain monitor testing at your side ?

As for the Aux log debug,

• You can enable Aug log traffic monitor via BITEC_AUX_DEBUG parameter in Bitec software config.h. But we typically do this for Intel FPGA DP RX, I am not sure whether we can do it for DP Tx as in your use case or not
  • Assume it works, then you just need to open NIOS II shell while programming DP design into FPGA then it will auto capture all the AUX log traffic in NIOS II shell terminal
  • Then you can help me to capture the raw Aux log for both SST and MST monitor
  • The challenging part will be hard to decode the raw Aux log
• Assume we are dealing with signal integrity issue here, easiest way will be to try out different brand DP cable, preferable shorter cable to improve the signal quality.

Thanks.

Regards,

dlim

[Deshi_Intel]

Hi Adam,

I have not hear back from you for few weeks.

Any update from your side.

Thanks.

Regards,

dlim

[Deshi_Intel]

HI Adam,

Understood that you could be busy with other higher priority project.

This is fine but I also wanted to let you know I can't let the case idle for too long without any activity update.

Therefore, I will proceed to close this existing case first.

Feel free to post new forum thread when you are free to resume the debug discussion again then Intel agent will continue to support you.

Thanks.

Regards,

dlim