I am using Cyclone III FPGA (EP3C55F484I7) for my design and Quartus II version 10 software.
In my RTL design, I am using division logic (signed data / integer). Currently, I am using / operator and its consuming lot of logic. This leads to timing violation. I trying to find Divider IP for this operation. Can you help for the same. How can I implement so that timing violation can be fixed. clk used is 24MHz.
There should be an LPM_divide megawizard for you to be used. Can you double check on this.
Also, I would suggest you use the Q13.1 version that last support CIII
Your frequecies running is not high. can you attached your design.qar for me to look into the violation. Basically, you will need to go though the training before do timing closure.
you may click on the follow on and Prerequisites link as well.
LPM_DIV is not there in the Quartus 10. I will check in 13.1. Sorry, I can't share you the qar as it is custom project. Briefly i can explain like from ADC data is acquired in signed format. Then this signal is multiplied with integer constant and then divided by a integer constant. When I ran STA, there is a huge data delay from F/F output of Multiplier to F/F input of Divider. The delay is 216ns. so slack is about -172ns.
You can try on the LPM_DIV on Q13.1 usually, it should not have problem on the timing closure if you use the IP provided.
Let me know if you still face problem after using the IP.