Do you use LPMs for your LFSRs?

[Altera_Forum]

I want to implement an LFSR as a means of generating random numbers but I'm not sure whether to use an LPM or just code it in a process. I would be interested to hear how you choose to implement them and if possible, why? I considered using either LPM_SHIFTREG or altshift_taps but I'm not sure how suitable they are. Many thanks

[Altera_Forum]

Either way you end up with shift register. 

Inference is easier and portable.   example --    signal shift_reg : std_logic_vector(33 downto 1);    process(reset,clk) begin if reset = '1' then shift_reg <= '0' & x"28EA5CB1"; -- seed elsif rising_edge(clk) then shift_reg(1) <= shift_reg(20) xor shift_reg(33); -- taps shift_reg(33 downto 2) <= shift_reg(32 downto 1); -- shift end if; end process;   the final output could be any number of bits you choose from the shift_reg however, my favorite method is read a text file.

[Altera_Forum]

Thanks again Kaz. I can't quite see where I was going wrong 

process(reset,clock) begin if reset = '1' then shift_reg <= "0001"; -- seed elsif rising_edge(clock) then shift_reg(1) <= shift_reg(0) XOR shift_reg(3); -- taps shift_reg(2) <= shift_reg(1); -- shift shift_reg(3) <= shift_reg(2); end if; output <= shift_reg; end process;  When I simulate this the output is always 1?

[Altera_Forum]

Probably your xor results in 1 always. 

You need to use standard proven register lengths and taps.  There is plenty of literature for various sizes and taps. e.g.one from xilinx: google xilinx LFSR   also note your feedback point should be at one end rather than 2nd stage

[Altera_Forum]

I changed the code to reflect a 4-bit LFSR that I know should step through all possible combinations, i.e. maximal length.  

process(reset,clock) begin if reset = '1' then shift_reg <= "0001"; -- seed elsif rising_edge(clock) then shift_reg(1) <= shift_reg(0) XOR shift_reg(3); -- taps shift_reg(2) <= shift_reg(1); -- shift shift_reg(3) <= shift_reg(2); shift_reg(0) <= shift_reg(3); end if; output <= shift_reg; end process;  It still does not seem to work though.

[Altera_Forum]

It looks like a correct implementation of x^4 + x^3 + 1. How did you test it?

[Altera_Forum]

By using the simulator within Quartus, I just ran the simulator, expecting to see 'output' change value each clock cycle but it is a constant value of '1'. It seems that the output sticks at whatever value I set the seed to be, i.e. a seed of 1111 resuts in a constant output of 15.

[Altera_Forum]

Your feedback point should be stage 0 not stage 1

[Altera_Forum]

according to xilinx doc a 4 bit shift register should have taps at 3,4 

 shift_reg(0) <= shift_reg(2) xor shift_reg(3); shift_reg(3 downto 1) <= shift_reg(2 downro 0);

[Altera_Forum]

--- Quote Start ---  It seems that the output sticks at whatever value I set the seed to be, i.e. a seed of 1111 resuts in a constant output of 15.  --- Quote End ---   The design is showing a perfect LFSR sequence of length 15 in simulation. I guess you missed to release the reset signal - or supplied no clock.    --- Quote Start ---  according to xilinx doc a 4 bit shift register should have taps at 3,4  --- Quote End ---   This is a different form of the same sequence.

[Altera_Forum]

--- Quote Start ---  Thanks again Kaz. I can't quite see where I was going wrong  process(reset,clock) begin if reset = '1' then shift_reg <= "0001"; -- seed elsif rising_edge(clock) then shift_reg(1) <= shift_reg(0) XOR shift_reg(3); -- taps shift_reg(2) <= shift_reg(1); -- shift shift_reg(3) <= shift_reg(2); end if; output <= shift_reg; end process;When I simulate this the output is always 1?  --- Quote End ---    This is a perfect implementation of 4-bits LFSR. If it stays at 1, check your reset signal.  Good luck, Ton

[Altera_Forum]

Thanks to all. I had made a stupid mistake, I had 'clock' in my process but I was actually using a different (reduced) clock in my simulation. Once I corrected that it worked perfectly. I have read up quite a lot on LFSRs so it was really bugging me!:rolleyes: Thanks again. This forum is invaluable.

[Altera_Forum]

Apologies for some confusion I caused about the two forms of lfsr. There are two equivalent types(Fibonacci and Galois). I was thinking only of Fibonacci type with taps feeding back onto first stage.