Documentation about resource usage of Altera cells

[Altera_Forum]

Dear Forum, 

  Xilinx has very good document - "Libraries Guide", about the netlist cells resource usage.   That document explains all standard cells used for synthesizing the design, and how many FPGA logic unit they are going to take after implementation. Please see the example of that file attached.   Do you know if Altera has similar document?  Please help, ThanksHayk

[Altera_Forum]

That "Libraries Guide" document looks like it's at least 15 years old. I don't think there's anything equivalent to that from either vendor these days. However, they both provide information on the resources used by IP blocks (Megafunctions). If you're trying to estimate whether a design will fit in a particular device you need to operate at a higher level than library primitives.

[Altera_Forum]

Now, most concerns for resource usage are with memories and DSPs. LUTs and Registers are so abundant that they are not usually the limiting factor.

[Altera_Forum]

The Library Guide is definitely nice and Altera doesn't really have an equivalent. They tend to have designers build IP at a more general level, e.g. create a 2-Port RAM that is the size you want and let the tools build it out of the low-level primitives, rather than giving you a long list of primitives and having you manually stitch them together into what you want. I prefer that flow(and Xilinx allows it in many cases too with LogicCore), but there are times where occasionally you want the lowest level primitive that matches hardware to custom build something.  

Anyway, I start in the tools and use the MegaWizard(pre q14.0) or IP Catalog(q14.0+) and browse for what I want.