Does Intel publish a MAX based solution for configuring a Cyclone IV using FPP?

[Oliver_I_Sedlacek]

I think I'm going to have to switch from AS configuration to FPP configuration for my Cyclone IV GX 110 PCIe design to meet the boot time requirement. Is there a solution I can just drop in rather than having to roll my own? The Cyclone 10 GX development kit does something like this. My priority is to have something simple so I don't need to spend ages debugging it.

[FvM]

Hi,
Parallel Flash Loader IP does just what you want.

[Oliver_I_Sedlacek]

Lots of develoment required by the look of that, which gets me back to wanting a real world example. Looks really risky if I don't know what the schematic should look like.

[NurAiman_M_Intel]

Hi,

You can use PFL IP for that. You can refer to board resource in link below as it uses PFL IP:

https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=56&No=756&PartNo=4#contents

Regards,

Aiman

[NurAiman_M_Intel]

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