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Don't work ALTDDIO_OUT for Cyclone5

Hello, dear friends


I use 5CGXFC5C6F23I7


I am using IP ALTDDIO_OUT in my project with triple speed ethernet to generate ETH_GTX_CLK


I carry it out as follows:

wire eth1_pll_clk_2p5; wire eth1_pll_clk_25; wire eth1_pll_clk_125; pll eth1_pll_inst ( .rst ( !any_rst_n ) ,.refclk ( CLOCK_25_FPGA ) ,.outclk_0 ( eth1_pll_clk_2p5 ) ,.outclk_1 ( eth1_pll_clk_25 ) ,.outclk_2 ( eth1_pll_clk_125 ) ,.outclk_3 ( ) ,.outclk_4 ( ) ); wire eth1_mdio_oen; wire eth1_mdio_out; wire eth1_mode; wire eth1_ena_10; reg eth1_tx_clk; eth_altddio_out eth1_altddio_out_inst ( .aclr ( !any_rst_n ), .datain_h ( 1'b1 ), .datain_l ( 1'b0 ), .outclock ( eth1_tx_clk ), .dataout ( ETH1_GTX_CLK ) );   always @(*) begin if (any_rst_n == 1'b0) eth1_tx_clk <= 1'b0; else if (eth1_mode) eth1_tx_clk <= eth1_pll_clk_125;// GbE Mode = 125MHz clock else if(eth1_ena_10) eth1_tx_clk <= eth1_pll_clk_2p5;// 10Mb Mode = 2.5MHz clock else eth1_tx_clk <= eth1_pll_clk_25; // 100Mb Mode = 25MHz clock end

code altddio_out:

module eth_altddio_out ( aclr, datain_h, datain_l, outclock, dataout);   input aclr; input [0:0] datain_h; input [0:0] datain_l; input outclock; output [0:0] dataout;   wire [0:0] sub_wire0; wire [0:0] dataout = sub_wire0[0:0];   altddio_out ALTDDIO_OUT_component ( .aclr (aclr), .datain_h (datain_h), .datain_l (datain_l), .outclock (outclock), .dataout (sub_wire0), .aset (1'b0), .oe (1'b1), .oe_out (), .outclocken (1'b1), .sclr (1'b0), .sset (1'b0)); defparam ALTDDIO_OUT_component.extend_oe_disable = "OFF", ALTDDIO_OUT_component.intended_device_family = "Cyclone V", ALTDDIO_OUT_component.invert_output = "OFF", ALTDDIO_OUT_component.lpm_hint = "UNUSED", ALTDDIO_OUT_component.lpm_type = "altddio_out", ALTDDIO_OUT_component.oe_reg = "UNREGISTERED", ALTDDIO_OUT_component.power_up_high = "OFF", ALTDDIO_OUT_component.width = 1;     endmodule



after synthesis, I see at RTL level that this block is present in the project, all the inputs and outputs are set up by Quartus, but at the same time, when I look at real hardware through signaltab, I do not see this output, or rather it hangs at a constant 0, also I do not see oscilloscope generation from a given cortex


at the same time, the eth1_tx_clk signal switches and issues a clock as it should, if you start it directly:

assign ETH1_GTX_CLK = eth1_tx_clk;

then the shred appears on ETH1_GTX_CLK, but if it is output via ALTDDIO_OUT, then it is not


what could be the problem?

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I saw article

how i can saw picture on signaltap from altddio_out on CYCLONE5?

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