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Valued Contributor III
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Downloading previous versions of documents

I am trying to download the Altera Verification IP Suite User Guide Version 2.0 January 2011 and its accompanying design file. But I am being directed to the latest Version 3.0 and design file if I use the link below: 

http://www.altera.com/literature/ug/ug_avalon_verification_ip.pdf 

 

Is there a server with all previous versions of a document? I need the older version because the new one's tutorial is making use of QSys to verify a device with Avalon-ST, but I want to use SOPC Builder instead. I have not moved to QSys yet.
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Valued Contributor III
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Re: Downloading previous versions of documents

I think these are the previous versions. 

 

They were downloaded for either version 10.0 or 10.1, I forget which. 

 

Cheers, 

Dave
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Valued Contributor III
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Re: Downloading previous versions of documents

if possible, please feed this back to Altera. i have had similar problems

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Re: Downloading previous versions of documents

Thanks for the files Dave. Have you just dowloaded them from somewhere or do you just happen to have these files on your computer?  

 

To get to the verification tool itself, I was able to run the tutorial files. Now I want to do the same thing on my own component which has Avalon ST interface. I followed all the steps until I reach page 13-5, Step 11: 

 

'In the Compile Source Files dialog box, select st_bfm_top.v and click Compile. Next select st_bfm_sopc.v and click Compile. Finally, select st_bfm_test.v and click Compile.' 

 

Do I have to manually write these top level test modules for my component or can they be automatically generated? If the latter, how? 

 

Thanks
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Valued Contributor III
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Re: Downloading previous versions of documents

 

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Have you just dowloaded them from somewhere or do you just happen to have these files on your computer?  

 

--- Quote End ---  

I had copies on my computer. 

 

 

--- Quote Start ---  

 

To get to the verification tool itself, I was able to run the tutorial files. Now I want to do the same thing on my own component which has Avalon ST interface. I followed all the steps ... 

 

--- Quote End ---  

Ignoring the VIP manual, here's what I do. I create an SOPC System with the Avalon BFM components, and then I let Quartus generate the simulation scripts for me (check the checkbox in SOPC Builder before clicking generate), eg., for a system called sopc_builder, a folder called sopc_builder_sim will be created in your project folder. Within that folder is a setup_sim.do script. Use this as a template for a new Tcl script to build the sopc_system files. Throw everything else away. 

 

Within the generated sopc_system.v file, there is a testbench. Ignore it, its useless (well, mostly useless, see the comment below). 

 

Create your own SystemVerilog testbench and instantiate a copy of the sopc_system. Use the hierarchical path to the BFMs to call their Verification IP API functions. 

 

I've only been working with Avalon-MM BFM masters, but this technique should work with Avalon-ST BFM masters too. 

 

The key thing to understand is that the Verification Suite cannot read your mind, so the automatic testbench it provides is pretty simple, but only because it has to be. Just think of it as a tool compilation test, i.e., you can build the design with Modelsim and vsim it, but it does not do anything interesting, eg., like actually test your design 🙂 

 

Cheers, 

Dave
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Re: Downloading previous versions of documents

 

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I create an SOPC System with the Avalon BFM components, and then I let Quartus generate the simulation scripts for me (check the checkbox in SOPC Builder before clicking generate), eg., for a system called sopc_builder, a folder called sopc_builder_sim will be created in your project folder. Within that folder is a setup_sim.do script. Use this as a template for a new Tcl script to build the sopc_system files. Throw everything else away. 

 

Within the generated sopc_system.v file, there is a testbench. Ignore it, its useless (well, mostly useless, see the comment below). 

 

Create your own SystemVerilog testbench and instantiate a copy of the sopc_system. Use the hierarchical path to the BFMs to call their Verification IP API functions. 

 

 

--- Quote End ---  

 

 

Thanks for the suggestions Dave. I've followed the initial steps but got lost at the stage of creating my own SystemVerilog testbench because I don't how how to write it. I looked at SystemVerilog tuts and I could only write the lines below. Could anybody give a few pointers on how to do the full testbench code? 

 

// console messaging level `define VERBOSITY VERBOSITY_INFO //BFM related parameters `define ST_SYMBOL_W 8 `define ST_NUMSYMBOLS 1 `define ST_CHANNEL_W 1 `define ST_ERROR_W 1 `define ST_READY_LATENCY 0 //local parameters `define ST_DATA_W `ST_SYMBOL_W * `ST_NUMSYMBOLS module learn_verification_ip_test(); import verbosity_pkg::*; endmodule  

 

The module I want to test is a University Program IP module called Video Edge Detection (see attachment) which takes in 8-bit values and outputs 8-bit values as well. But the module takes in a series of data values to represent a frame of data values. I found out that $readmemh is useful in my case. I want to be able to read the data values from a text file using $readmemh, and write the results also back to another text file. Will I be able to do that in SystemVerilog and BFM? 

 

As I couldn't get anywhere with the BFM components, I tried creating a testbench for that component as below without using BFM or SystemVerilog. But here again, I don't think it is good as I am not getting any meaningful results when I try to run it in ModelSim. Any suggestion is greatly appreciated. 

 

// Simulation tool : ModelSim-Altera (Verilog) // `timescale 1 ps/ 1 ps module main_edge_detection_streaming_vlg_tst(); // constants // general purpose registers reg eachvec; // test vector input registers reg clk; reg in_data; reg in_empty; reg in_endofpacket; reg in_startofpacket; reg in_valid; reg out_ready; reg reset; // wires wire in_ready; wire out_data; wire out_empty; wire out_endofpacket; wire out_hw_counter; wire out_startofpacket; wire out_valid; // assign statements (if any) main_edge_detection_streaming i1 ( // port map - connection between master ports and signals/registers .clk(clk), .in_data(in_data), .in_empty(in_empty), .in_endofpacket(in_endofpacket), .in_ready(in_ready), .in_startofpacket(in_startofpacket), .in_valid(in_valid), .out_data(out_data), .out_empty(out_empty), .out_endofpacket(out_endofpacket), .out_hw_counter(out_hw_counter), .out_ready(out_ready), .out_startofpacket(out_startofpacket), .out_valid(out_valid), .reset(reset) ); reg storage_values ; //153600 values for 640x240 image integer fileId, fileOutput; initial begin // code that executes only once clk = 1'b1; // Do the hexadecimal reads from the txt file $readmemh("hexval_test_1d.txt", storage_values); // ouput result will be sent to a text file fileOutput = $fopen("result_sobel.txt", "w"); reset = 1'b0; in_empty = 1'b1; in_startofpacket = 1'b1; in_valid = 1'b1; in_endofpacket = 1'b0; //in_ready = 1'b1; //Stop after 1536000 clock cycles ??# 1536000 in_endofpacket = 1'b1; $display("Running testbench"); end // Control the clock signal initial begin forever# 5 clk = ~clk; end integer i; initial begin for (i=0; i < 153600; i=i+1) begin @(posedge clk); in_data = storage_values; $fwrite(fileOutput,"%d\n",out_data); end @eachvec; end endmodule
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Re: Downloading previous versions of documents

Here's a verification example. The SOPC System contains an Avalon-MM BFM master, an on-chip RAM, and a PIO component. The readme.txt file explains how to rebuild the system. 

 

The SystemVerilog testbench sopc_system_tb.sv in the folder sopc_system_sim/ shows you how to create an instance of your design and issue the BFM calls. 

 

Cheers, 

Dave
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Re: Downloading previous versions of documents

Thanks for the example. I will try to learn as much as I can from this. But at step (d) when I type s, I get the following error message: 

 

# ** Error: (vsim-3010) - Module 'sopc_system_tb' does not have a `timescale directive in effect, but other modules do.# Region: /sopc_system_tb/dut/the_master_bfm/master_bfm  

 

Any suggestion on how to handle this error? 

 

Thank you.
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Re: Downloading previous versions of documents

 

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But at step (d) when I type s, I get the following error message: 

 

# ** Error: (vsim-3010) - Module 'sopc_system_tb' does not have a `timescale directive in effect, but other modules do.# Region: /sopc_system_tb/dut/the_master_bfm/master_bfm Any suggestion on how to handle this error? 

 

 

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The vsim command should have a '-t ps' option in its command line, so it should work. I've seen this as a warning in simulations, but not as an error, so perhaps there is an option that can be changed to suppress this error. Which version of Modelsim are you using, i.e., what do you get for vsim -version? 

 

Note that the error is in the Altera-generated BFM code. 

 

Cheers, 

Dave
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Valued Contributor III
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Re: Downloading previous versions of documents

I am using ModelSim Altera Starter Edition vsim 6.6c Simulator 2010.08 Aug 24 2010. 

 

I don't get the error if I 's' after using do on the generated setup_sim.do. 

 

Assuming we get this error cleared, do you think I can still achieve what I'm trying to do, i.e. read values from text file, simulate component, and save output to another text? In your sopc_system_tb.sv file, I can see that I will have to modify the two tasks avalon_write_single and avalon_read_single to be able to do what I want, but I don't know how to do that yet and it does seem a bit complicated for a relatively simple thing to do if I was testing a code in C for example. 

 

I was just wondering whether this is the best way for me to test a hardware module. Or perhaps everything is complicated with FPGAs... damn I should have stuck with C coding 🙂
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Re: Downloading previous versions of documents

 

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I am using ModelSim Altera Starter Edition vsim 6.6c Simulator 2010.08 Aug 24 2010. 

 

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I'll try it with a Modelsim-ASE version and see what I get. 

 

 

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Assuming we get this error cleared, do you think I can still achieve what I'm trying to do, i.e. read values from text file, simulate component, and save output to another text? 

 

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Yep, absolutely. SystemVerilog is both a programming language and a hardware language. Whatever you can do in C/C++, there is something similar in SystemVerilog. You can even link C to SystemVerilog ... but I'm not sure if Modelsim-ASE supports that. 

 

 

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In your sopc_system_tb.sv file, I can see that I will have to modify the two tasks avalon_write_single and avalon_read_single to be able to do what I want, but I don't know how to do that yet and it does seem a bit complicated for a relatively simple thing to do if I was testing a code in C for example. 

 

I was just wondering whether this is the best way for me to test a hardware module. Or perhaps everything is complicated with FPGAs... damn I should have stuck with C coding 🙂 

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I suspect you were just doing simple C code.  

 

The real world is much more complicated. Testing code at the component level, and then at the system-level takes extra effort. But that effort pays off big-time when you do not have to debug difficult problems; you avoided them by putting in the extra work up-front. 

 

For example, when you write C code, do you write 'unit tests' to ensure that every C function does what it is supposed to do given correct inputs and incorrect inputs? Do you have a 'make check' build command that confirms every test passes. Do you have a continuous-integration build system, where your system-level code is checked out of a code repository and is continually built and checked ... The complexity of real-world development occurs everywhere 🙂 

 

Cheers, 

Dave
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Re: Downloading previous versions of documents

 

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# ** Error: (vsim-3010) - Module 'sopc_system_tb' does not have a `timescale directive in effect, but other modules do.# Region: /sopc_system_tb/dut/the_master_bfm/master_bfm Any suggestion on how to handle this error? 

 

--- Quote End ---  

To the top of sopc_system_tb.sv add the line 

 

`timescale 1ns / 1ps Then Modelsim-ASE was happy for me. To build and run the code, on the Modelsim command line I used the commands; 

do setup_sim.do s vlog -sv sopc_system_tb.sv vsim -t ps -novopt +nowarnTFMPC sopc_system_tb do sopc_system_tb.do run -a Enjoy! 

 

Cheers, 

Dave
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Re: Downloading previous versions of documents

Many thanks again Dave. The timescale line fixed it. Yes you are right I have done only basic coding so far, nothing real world. One day perhaps... if I manage to survive all the FPGA learning. It's just that I've started learning about hardware programming around 4 months ago, but I feel that I spend most of my time learning how to use tools rather than actually doing anything productive. First it was Quartus, then SOPC, then NIOS SBT, now ModelSim.... But I guess it's the way to learn step by step. 

 

Talking about learning, my current testbench in sv for my ST component doesn't do anything yet apart from just displaying a test message. I am trying to write an actual testbench with meaningful inputs.. be prepared for more beginner questions soon 🙂
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Re: Downloading previous versions of documents

 

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Yes you are right I have done only basic coding so far, nothing real world. One day perhaps... if I manage to survive all the FPGA learning. It's just that I've started learning about hardware programming around 4 months ago, but I feel that I spend most of my time learning how to use tools rather than actually doing anything productive. First it was Quartus, then SOPC, then NIOS SBT, now ModelSim.... But I guess it's the way to learn step by step. 

 

--- Quote End ---  

Trust me, it does not get any easier ... the tools change almost as fast as you learn them ... and then a new FPGA comes out and you have to start reading data sheets from-scratch again ...  

 

It does make for good job security though 🙂 

 

 

--- Quote Start ---  

 

Talking about learning, my current testbench in sv for my ST component doesn't do anything yet apart from just displaying a test message. I am trying to write an actual testbench with meaningful inputs.. be prepared for more beginner questions soon 🙂 

--- Quote End ---  

There are really two types of testbenches; interactive and automatic. An interactive testbench is one that exercises your design, but does not really check anything, eg., injects noise into a digital filter, writes the results to file, and then finishes. In this type of design, its up to you to check the results using say MATLAB to check the power spectrum. An automated testbench also checks the result, i.e., you have a "golden reference" output data file, and the testbench checks that the golden reference results were reproduced by the design. This last testbench is very useful as you don't need to look at the design once you've finished it, so long as you run the testbench, eg. using a makefile "make check" command. If you change a component that the design uses, and you break it, when you run the testbench it will fail, and you can go and fix the bug you just introduced. 

 

Keep that in mind while designing. 

 

Cheers, 

Dave
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Re: Downloading previous versions of documents

Cheers Dave. I am doing the interactive testbench for now but I am having problems with reading the input data file. I have an array of size 153600 bytes that I save as follows in matlab: 

 

fid = fopen('image_binval.bin', 'w'); fwrite(fid, data_image_1d,'uint8');  

 

The main parts of my current systemverilog testbench file are shown below. I am just making sure the correct values are being read in. When I run it in modelsim, src_transaction.data shows the correct data values in the wavewindow until variable i reaches 57672. After that, it just displays a x in between red lines. I can't find where I am going wrong. Any help please? 

 

`define NUMBER_OF_PIXEL_VALUES 153600 `timescale 1ns / 1ps module sopc_system_tb(); import verbosity_pkg::*; // 50MHz clock period localparam time CLK50_PERIOD = (1.0e9/50.0e6)*1ns; // Clock and reset logic clk; logic rstN; // Avalon ST typedef logic AvalonSTData_t; reg storage_values ; //153600 values for 640x240 image integer fileInput, r; //the ST transaction is defined using SystemVerilog structure data type typedef struct { int idles; //idle is not part of Avalon ST signal, it is used in BFM only bit startofpacket; bit endofpacket; AvalonSTData_t data; } transaction_struct; transaction_struct src_transaction, snk_transaction; int i, j; // 50MHz system clock initial clk = 1'b0; always # (CLK50_PERIOD/2) clk <= ~clk; // SOPC system -Set up the Dut sopc_system dut ( .clk_0 (clk), .reset_n (rstN) ); // Stimulus // ------------------------------------------------------------ initial begin // Initialize input and output text files fileInput = $fopen("image_binval.bin", "r"); r = $fread(storage_values, fileInput, 0, `NUMBER_OF_PIXEL_VALUES-1); // Initialize the BFM // ------------------------------------------------------------ set_verbosity(`VERBOSITY); `SRC.init(); `SNK.init(); rstN = 0; # 50ns rstN <= 1; // -------------------------------------------------------- $display("Simulation Start"); // -------------------------------------------------------- for (i = 0; i < `NUMBER_OF_PIXEL_VALUES; i++) begin @(posedge clk); src_transaction.idles = 0; src_transaction.data = storage_values; if (i == 0) src_transaction.startofpacket = 1; else src_transaction.startofpacket = 0; if (i == `NUMBER_OF_PIXEL_VALUES-1) src_transaction.endofpacket = 1; else src_transaction.endofpacket = 0; end end endmodule
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Re: Downloading previous versions of documents

 

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I am just making sure the correct values are being read in. When I run it in modelsim, src_transaction.data shows the correct data values in the wavewindow until variable i reaches 57672. After that, it just displays a x in between red lines. I can't find where I am going wrong. Any help please? 

 

--- Quote End ---  

I can't see anything obviously wrong. 

 

However, if you just want to check that data is being read in ok, change the loop to simply display the values read from the file, eg., something like 

 

logic val; for (int i = 0; i < `NUMBER_OF_PIXEL_VALUES; i++) begin @(posedge clk); val = storage_values; end And display val in the wave window. 

 

Cheers, 

Dave
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Re: Downloading previous versions of documents

 

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And display val in the wave window. 

 

 

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Yeps, I've tried that but still the same result after the counter reaches 57672. Could it be that I have reached some kind of limit with my ModelSim Starter Edition? The Altera website says the limit is 10,000 executable lines. I don't have this number of lines, but the main top module does call a few IP modules such as altshift_taps.. so it could be the case 😞 Can somebody please confirm this? 

 

Assuming I get the data reading to work, I have a question related to Avalon ST this time: Is my implementation of endofpacket correct?  

 

if (i == `NUMBER_OF_PIXEL_VALUES-1) 

src_transaction.endofpacket = 1; 

 

I am not too sure if end of packet means the end of the whole of the data to be transferred.  

 

Also, how do I get output values from the device under test to go to snk_transaction.data?
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Re: Downloading previous versions of documents

 

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Yeps, I've tried that but still the same result after the counter reaches 57672. Could it be that I have reached some kind of limit with my ModelSim Starter Edition? 

 

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Post a .zip file with source and a simulation script, and I'll try it in SE. 

 

 

--- Quote Start ---  

 

Assuming I get the data reading to work, I have a question related to Avalon ST this time: Is my implementation of endofpacket correct?  

 

if (i == `NUMBER_OF_PIXEL_VALUES-1) 

src_transaction.endofpacket = 1; 

 

I am not too sure if end of packet means the end of the whole of the data to be transferred.  

 

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You won't break anything in simulation, so your best bet is to just try the obvious and see what happens. I haven't tested ST interfaces with the verification suite, so cannot offer any experience. 

 

 

--- Quote Start ---  

 

Also, how do I get output values from the device under test to go to snk_transaction.data? 

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I would look at the Avalon-ST example provided in the verification IP suite. Hopefully they show how to use the ST API and connect it to something. 

 

I think the main thing to keep in mind, is just to try stuff, look at the waveform view, and try and clear up anything that is red. The other thing to do is look at the source code for the verification functions.  

 

Cheers, 

Dave
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Re: Downloading previous versions of documents

Thanks for your continuous support Dave. I don't think this problem is related to ASE, because I have just installed the full edition (I didn't even know we had this license!) and I still face the same problem. The error is happening with the $fread command. For example, in the following line, read_index stays at 57671 when I look at the waveform window. It's expected to be NUMBER_OF_PIXEL_VALUES-1 instead. 

 

read_index = $fread(storage_values, fileInput, 0, `NUMBER_OF_PIXEL_VALUES-1);  

 

I then tried to use $readmemb but not much luck with this either... it sent modelsim crashing when I tried to simulate it! I'm attaching the zip file which contains the simulation script(sopc_system_tb.sv) and the input data file(image_binval.bin) in folder sopc_system_sim. Could you have a go at reading the data file please? It contains 153,600 values of unsigned 8-bit integers.
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Re: Downloading previous versions of documents

Hmmm.. just forget my previous message concerning $fread. I managed to get it working by adding a "rb" instead of "r" in $fopen. Dow!! I feel so stupid 🙂 

 

fileInput = $fopen("image_binval.bin", "rb"); 

 

OK, I'll start reading the Avalon ST documentation now and try things.. real work starts! Hopefully somebody with experience of ST verification will turn up on that forum soon too.
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