Driving Multiple FPGAs and Fanout (Cyclone III)

Altera_Forum · ‎08-03-2009

Hi,

I have a design that will comprise of 11 FPGA boards: 10 slaves and 1 master and each board is having one cyclone III FPGA. The communication between master and slaves is via a simple SRAM protocol (with addr, data, WR/RD and CS). All boards will be interconnected together on a backplane board, with about 1 inch apart.

According to the electrical specifications, the input leakage current of each pin is only 10uA. Therefore, in the case of LVTTL with 4mA drive strength, theoretically one master could drive up to 400 slaves? Is this too good to believe? Also, overshoot voltage could be a problem if signals are not terminated. Altera recommended 33R series resistor on each line. Does anyone have similar experience on this?

I also would like to know what is the real benefit of using LVCMOS apart from LVTTL.

Any recommendation is much appreciated.

Altera_Forum · ‎08-03-2009

Hi,

It is a lot more complex than you have suggested, do a web search for VME bus and use some VME bus drivers to drive your backplane. VME is a standard protocoll for use in your type of application and it would save you a lot of design costs.

Uk Fixer

Altera_Forum · ‎08-03-2009

You'll have to face the same signal integrity problems as with any other unterminated data bus system. Particularly the stubs loaded with the FPGA I/O capacitance will cause serious signal reflections. Series resistances, either at the chips or near the board connector can help to reduce it. You should use a moderate bus speed anyway.

There's no principal difference between LVTTL and LVCMOS I/O standard on the FPGA side, it's just a different way to calculate the I/O drive strength according to the different thresholds involved with the standard.

P.S.: From existing single ended bus standards, Cyclone III supports 3.3V PCI and PCI-X. This is a way to provide a specified standard without external bus drivers.