Dual Configuration Intel FPGA IP Core Signals

[Sho2301]

Hi,

i have a few questions regarding the signals of this IP Core. 

Am i correct to assume that the avmm_rcv_address sets the Offset for the register i want to read and write from, so that with avmm_rcv_writedata i can then write in that offset register.

For a example, would it be correct that if i wanted to enable the config_sel overwrite and set the config_sel to CFM 0 i would need to write the following:

avmm_rcv_address <= "001";

avmm_rcv_writedata (1 down to 0) <= "01"

avmm_rcv_writedata (31 down to 2) <= (others => '0');

I assume the avmm_rcv_read & avmm_rcv_write are used for write/read busy flags?

Thank you for your assistance

Regards,

Sho

[FvM]

Hi,
the MAX10 Configuration User Guide refers to Avalon Interface Specification https://www.intel.com/content/www/us/en/docs/programmable/683091/22-3/introduction-to-the-interface-specifications.html for details of AVMM interface. It should answer your questions about the function of specific signals. You don't necessarily need the info when you use Platform Designer to connect the configuration IP because all signals are wired automatically. But you may need it when you write your own AVMM master to drive the interface.

Regards
Frank

[RichardTanSY_Altera]

Thank you Fvm for answering.

Hi @Sho2301 

I believe Fvm has answered your inquiry.

Do you have further inquiries regarding this case ?

Regards,

Richard Tan

[RichardTanSY_Altera]

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