Dual Port Ram problems : Synthesizes error with one or two clock signals

[Altera_Forum]

Hello, 

I was running in a problem and can't find a way out . Although there are already a lot of posts concerning problems with dual port rams, I couldn't found a solution. I am using a DE1 board, based on the CyclonII EB2C20F484C7, using Quartus 9.1, SP2. My goal is a dual clocked true dual port ram to be able to read/write on both ports. I was trying the ALTERA altsynram and altpram megafunction with the frustrating result: Selected device has 52 RAM location(s) of type M4K. However, the current design needs more than 52 to successfully fit. I still can't understand this, because I striped down my design to: 6200 16 Bit words which results in a usage of 25 x M4K blocks from 52 available M4K blocks.  Anyway, I decided to write my own dual port ram code in verilog (See my posted code) . First time, it was looking good: I was able to write to port A and read from port A and I was also able to read the written data from port B ..... BUT--- I was not able to write data to port B. With reference to to the post from ammar ( September 23rd, 2010), I was in th opinion that my problem is related to the usage of 2 clocks. I did write a clock-domain- mux ( code also posted ) to bring my dual port ram design up and running with one clock source . ..... BUT--- the same problem. synthesizes error   I do not know how to proceed now any more and every help is very welcome.  Datails concerning my project can be obtained from my homepage.  My questions:  A) Is my verilog code wrong ?  B) Is the CyclonII EB2C20F484C7 to small or did I use the wrong libraries ?  May be you also have other ideas , how I can solve the problem differently     Many thanks in advance, Reinhard 

[Altera_Forum]

I reproduced this problem. It says this feature of dual clock dual port is not supported in current device and current software. 

 Then I tried single clock and it was successful and used 32 blocks of M4ks.  Thus you may need to use one clock plus a dc fifo

[Altera_Forum]

--- Quote Start ---  I reproduced this problem. It says this feature of dual clock dual port is not supported in current device and current software.  Then I tried single clock and it was successful and used 32 blocks of M4ks.  Thus you may need to use one clock plus a dc fifo  --- Quote End ---    Thank you for your reply. I am not passed with my single clock dual port implementation. May you provide me plaese a working dual port ram code or do you have plaese a note for me, why my code is not working

[Altera_Forum]

I simply went to megawizard, chose dual port ram, used 16 bits width x 6200 and set to single clock. 

 Here are some info on my compilation:  Quartus II Version 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition Revision Name test Top-level Entity Name test Family Cyclone II Device EP2C20F484C7 Timing Models Final Met timing requirements Yes Total logic elements 38 / 18,752 ( < 1 % ) Total registers 4 Total pins 93 / 315 ( 30 % ) Total virtual pins 0 Total memory bits 99,200 / 239,616 ( 41 % )

[Altera_Forum]

Ok, I will try this way. 

Thanks for the info.

[Altera_Forum]

It's always instructive to read the Quartus error message completely: 

   --- Quote Start ---  Error: M4K memory block WYSIWYG primitive "altsyncram:altsyncram_component|altsyncram_fv42:auto_generated|ram_block1a27" utilizes the dual-port dual-clock mode. However, this mode is not supported in Cyclone II device family in this version of Quartus II software. Please refer to the Cyclone II FPGA Family Errata Sheet for more information on this feature.  --- Quote End ---    The interesting point is the reference to Cyclone II errata sheet. Cyclone II early revisions had a silicon bug that is handled by a workaround in Quartus, unfortunately doubling memory resource consumption for single port and not working with true dual port RAM at all.  Presuming you have EP2C20 Revison B chips, all you have to do is to add a synthesis parameter to your design settings. Use the below tcl line or enter it under default parameters. You should also refer to the Cycclone II errata sheet to learn more about the issue.  set_parameter -name CYCLONEII_SAFE_WRITE VERIFIED_SAFE  You can implement 13000 words DP RAM in your device using this settings.  Regards, Frank

[Altera_Forum]

Hello kaz and Frank, 

many thanks for the information. I was able to found a solution with your notes. True dual port ram with 2 clock is still a issue, but I could solve this issue based on my clock_domain_mux code. Works fine for me. Regards, Reinhard

[Altera_Forum]

FvM already found for you the trick (also given personal advice on reading errors - thanks to Frank). 

 add this statement:  set_parameter -name CYCLONEII_SAFE_WRITE VERIFIED_SAFE to your qsf  then it will support two clocks dual port ram

[Altera_Forum]

Feasibility of the solution depends on the used FPGA revision. With the old chips, you are stuck to single port and half RAM capacity. With recent Cyclone II parts, specifying SAFE_WRITE is mandatory to get hold of the full RAM capacity.

[Altera_Forum]

Hello, 

you have provided the same info to use the Statement: set_parameter -name CYCLONEII_SAFE_WRITE VERIFIED_SAFE. It does not solve the dual-clock problem. I still receive the message : Error: M4K memory block WYSIWYG primitive "lpm_ram_dp0:inst4|altsyncram:altsyncram_component|altsyncram_1o12:auto_generated|ram_block1a16" utilizes the dual-port dual-clock mode. However, this mode is not supported in Cyclone II device family in this version of Quartus II software. Please refer to the Cyclone II FPGA Family Errata Sheet for more information on this feature. If I use my design, I will get sythesizes errors. Seems to be , on my DE1 board is an old version of chip installed. Anyway, I have a workaround. 

[Altera_Forum]

Obviously, the Quartus software can't determine the chip revision. It has to rely on your setting. I often used the SAFE_WRITE setting with Cyclone II and also checked it again with the standard DP MegaFunction. It definitely works. 

 I don't know what's wrong in your test. I append my test setup.  Regards,  Frank

[Altera_Forum]

Hi Frank, 

thanks for posting your setup. I will try it via import your setup in my environment. I am sure, the problem is related to myself. I am still a QUARTUS beginner...  Regards, Reinhard

[Altera_Forum]

Did you close the project before inserting text to the *.qpf file? Otherwise, the edit will be ignored and overwritten, when closing the project. Performing a tcl command or modifying settings in the IDE will take effect immediately.

[Altera_Forum]

Hello, 

the problem is fixed. Dual ported Ram with 2 clocks is up and runnig. The remaining problem is a feature of the EB2C20F484C7 with only 52 4K block. Many thanks for your help, especially to Frank. Regards, Reinhard

[Altera_Forum]

Thx~&#65281;I’ll try it&#65306;&#65289;:):) 

  --- Quote Start ---  It's always instructive to read the Quartus error message completely:     The interesting point is the reference to Cyclone II errata sheet. Cyclone II early revisions had a silicon bug that is handled by a workaround in Quartus, unfortunately doubling memory resource consumption for single port and not working with true dual port RAM at all.   Presuming you have EP2C20 Revison B chips, all you have to do is to add a synthesis parameter to your design settings. Use the below tcl line or enter it under default parameters. You should also refer to the Cycclone II errata sheet to learn more about the issue.   set_parameter -name CYCLONEII_SAFE_WRITE VERIFIED_SAFE   You can implement 13000 words DP RAM in your device using this settings.   Regards, Frank  --- Quote End ---