Dual port RAM read controls in CycloneIII

[Altera_Forum]

I don't seem to be able to search for a comprehensive reference on the Altera M9K memories for the Cyclone III. Where I find a decent reference for some aspects, I don't have them all described. 

 That are the nuances that make these signals diferent? - rden - rd_addressstall - rdclocken   The addressstall signals are illustrated in one reference as a feedback mux. Pleasant.   But does the rdclocken affect both the read address and registered q output?   Does the rden load the new address but keep the old value in the asynchronous output?   I'd love a solid description of these signals but the MegaWizard and the documentation I've found leave me wanting.   Thanks for any references or insights, - John

[Altera_Forum]

I guess you've already found the Cyclone III handbook. 

That's pretty much the main (only?) documentation I know of regarding the FPGA's low level details.  The Megawizzard is a separate matter. The Megawizzard offers abstract RAM modules, which may or may not be implemented using M9K blocks and abstract away the M9K low level details. So, best not look too much into that if you're looking into the low level details of the M9K blocks.