module my_counter(
input clk,
input reset_n,
input load,
input new_count,
output reg event
)
reg count_val;
reg counter;
always @(posedge clk)
if(load) count_val <= new_count;
always @(posedge clk or negedge reset_n)
if(!reset_n) counter <= 16'd0;
else if(!counter) counter <= count_val;
else counter <= counter - 16'd1;
endmodule
Jake
