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Dynamic Reconfiguration: reconfig_clk pin

Altera_Forum
Honored Contributor II
‎02-13-2012 11:51 PM
1,138 Views

Hello, I'm using the Cyclone IV's ALTGX_RECONFIG megafunction. I would like to know if there are any constraints on the clock that drives the reconfig_clk port? Does this clock need to be a differential clock to the FPGA?  

 

Currently I am using a single-ended clock and have connected it to CLKIO5/DIFFCLK_6P pin on the FPGA (EP4CGX150DF31). I'm not sure if it would be better to connect the clock on one of the REFCLK[0..2] pins.  

 

Thanks, 

joe
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Altera_Forum
Honored Contributor II
‎02-14-2012 12:10 AM
441 Views

the single ended clock should be fine

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