Dynamic Reconfiguration

Altera_Forum · ‎08-08-2007

Hi,

Do any of the Altera FPGAs offer dynamic reconfiguration abilities similar to that found on Xilinx which uses JBits.

Thanks

Altera_Forum · ‎08-08-2007

No.

They do offer dynamic reconfigurationm of certain elements within the FPGA, like the SerDes or the PLL's.

They also do have a rather solid full chip auto - reconfiguration mechanism if you have multiple configuration files you wish to load.

It is full chip load, not partial.

Altera_Forum · ‎08-08-2007

what are you trying to accomplish with the partial reconfiguration? there may be other ways.

Altera_Forum · ‎08-08-2007

Are you choosing an FPGA Vendor and does this have a high priority for making your decision? To my understanding it has always been a very flawed flow when trying to use it, and the slogan is that it will be fixed in the next release(like being a Cubs fan, wait until next year...) Note that Xilinx has has partial reconfiguration since the release of Virtex many, many years ago, and yet you still have to be accepted into the Early Access program to use it.

I'm sure some users have gotten it to work, but I work in the field with many customers and never ever run into this being used.

Now, this is complete hearsay, so please do your own diligence. And if you use JBITs and disagree with this, please let me know. I just don't want you to make an architectural decision based on something you can't get to work or just won't use in the end.

Altera_Forum · ‎08-09-2007

I attended a seminar at the Embedded Systems Conference 2007 in which Xilinx presented their partial dynamic reconfiguration. I got the feeling that it was available, but, as you said, still for early adopters.

If memory serves, the presentation showed an example with an FPGA that could do audio processing, and reconfigure a portion of itself to have either a low-pass filter, high-pass filter, or no filter.

During the presentation it occurred to me that dynamic reconfiguration does not seem to have many advantages over simply having two FPGA's, one of which can configure the other.