EP3C16 and EPCS16 config fail while JTAG mode succeed...

Altera_Forum · ‎12-10-2009

I am using EP3C16Q240C8 , and the configuration device is EPCS16

When I debug my project, I used the JTAG mode, and that's all right.

and download to the device EPCS16 is correct which is indicated by QuartusII 9.0. Since this, everything seems be all right.

BUT, I found that my 3C16 can't configure itself from the EPCS16.

after power on:

conf_done is always low

nconfig is always high

NCE is always low

and the nSTATUS appears a positive pulse every 60us

and the DCLK is the same as nSTATUS

and NCSO is reversedly nSTATUS......

it's so strange...

my MSEL[2..0] is 010, and i connect it directly to 3.3V ( VCCIO) .

and i check my .sch for hundred times and it's the same as ALTERA instructions.

Someone says that when he touch some pins with a probe, like conf_done or DCLK, it can configure again. but i try this method and it doesn't work......

I need help , please..

Altera_Forum · ‎12-10-2009

--- Quote Start ---

my MSEL[2..0] is 010, and i connect it directly to 3.3V ( VCCIO) .

and i check my .sch for hundred times and it's the same as ALTERA instructions.

--- Quote End ---

Strictly spoken, Altera suggest to pinstrap MSEL to VCCA for '1' in all Cyclone III documents. The suggestion repeats about 30(!) times in the device handbook.

So far about checking hundred times. If I remember right, the device handbook explains, that there's a risk to latch an invalid MSEL configuration, when VCCA is powered before VCCIO with your kind of MSEL connection. You may check your power supply design, if this can happen. In those cases, where VCCA is derived from VCCIO by a LDO, it can't happen. Apart from this special point, I don't see a particular explanation for the observed behaviour, provided all configurations pins are wired as they should.

Altera_Forum · ‎12-11-2009

Thrank you very much , FvM

I'll check right now

Altera_Forum · ‎12-11-2009

i can confirm that all the configurations pins are wired as they should.

and i changed the MSEL(1) to the VCCA ( 2.5V )

and then i found the same problem

after read the CycloneIII handbook i find that MSEL is powered by VCCINT(1.2V), and my VCCINT is derived from 2.5V ( VCCA ).

and i searched this forum,and i found this topic : http://www.alteraforum.com/forum/showthread.php?t=4168

and it's almost the same ...

but when i changed all the 10K pull ups to 5K , it's not ok..

Altera_Forum · ‎12-11-2009

by the way, my configuration device is far away from the EP3C16, the longest wire maybe 7000 mils(7 inches ) , and the handbook says that the maximun is 10 inches. so i think it's just ok for this distance....

Altera_Forum · ‎12-11-2009

7" is quite a lot. Generally, EPCS interface is more critical than JTAG. I never had a board with a distance larger than 2" to maximum 2.5". I can't predict, how the signal quality will be with that large distance, I'm also not sure, if Altera has actually tested the said 10".

Altera_Forum · ‎12-11-2009

It's hard for me to change the distance..

And I've browsed this forum and i found that many topics talked about this issue. Someone probed some pins and got solution but i can't, someone changed the pull-up to 4.7K and it worked but i can't , someone said that Quartus 9.1 had bug at AS mode but i'm using Quartus 9.0...

Altera_Forum · ‎12-14-2009

fixed ! i just removed those four 10pf capacitors which were related to the EPCS16 and EP3C16 device!

I'm so glad for that!

I think maybe the distance is the problem...becourse the handbook recommends that the 10pf capacitors must be placed as close to the FPGA as I can, but obviously, I did not see it.

So thanks everyone