Hi,i'm designing a power stage to my system where 3 EP5357HUI/LUI devices in parallel to produce voltages for FPGA. PowerSoCs are powered by first stage switcher which is built on TIs TPS61020 Boost-converter. I have a problems with PowerSoCs (occurring randomly from time to time, but very often, like 50% probability) that are: - output voltage is equal to input voltage or - input current of EP device is about 70mA RMS even without load and it constantly switches on and off. Output voltage is similar to sawtooth. configuration and layout is done very similar to recommendations in datasheet (there is no space for much creativity in designs like that): 4u7 MLCC on input and 22u MLCC on output pins, ENABLE, LLM, AIN, PIN tied together. I have one suspicion however, previous power stage has a soft-start with ramp time of about 2-3ms. PowerSoCs also behave similar when connected to laboratory power source and when I turn the voltage knob one way and another. It looks like the under-voltage protection and enable logic doesn't work as I assumed. Do You have any ideas for an easy fix, or have an idea what am I'm missing here?
I am working on a design that uses the EP5357HUI and we are also having the output voltage = input voltage problem. In our design Enable is tied through a 10k resistor to AVIN and PVIN. If we temporarily GND the Enable pin, then when Enable is released VOUTA = 1.8V as designed. We now suspect that Enable has to brought high AFTER AVIN and PVIN are ready. Is that correct?