EPCS Config via SOPC Builder component in normal user design

[Altera_Forum]

Hi, 

 I just want to make sure I have understood the documentation correctly and my plan can work. We want to update the bitstream in our EPCS16 + Stratix2 system respectively our EPCS64 + Stratix3 system remotely. Both are attached using Acitve Serial Configuration.  I want to use the EPCS Device Controller Core from SOPC_Builder but without a SOPC_Builder system. I think this should work, I have seen this before.  My main question is: The EPCS pins are not user pins, but from my understanding using the EPCS device controller core will allow me access. All I have to do then is to operate the interface as NIOS would do.  Do you see a problem with this?  Best regards flintstone

[Altera_Forum]

Hi, 

 not too much enthusiasm about this topic it seems ;) .  I've now found this sentence in the documentation:  "The core must be connected to a Nios II processor."  So this sounds like my plan will not work but why should it not work? If I manage to find out how NIOS operates the interface to this component what could be the the problem doing it with a custom VHDL design?  Of course, a problem would be if Quartus just would not synthesize the design for some reason.  Maybe somebody got an idea on this?  Best regards, flintstone

[Altera_Forum]

i would guess the Nios II "requirement" is based on the availability of the HAL drivers for the EPCS Controller. i'm sure you could reverse engineer what's going on between the C code and some SignalTap, but at some point a Nios II/e and an onchip RAM is going to make more sense

[Altera_Forum]

Hi, 

 the problem is that the boards are already there, they lack an external SRAM for NIOS (maybe the FPGA SRAM would suffice but we need it for other stuff, too) and keeping power consumption low on the boards is a very important thing for us. Therefore I don't want to implement a NIOS there only for the purpose of updating the flash, which should happen very infrequently while it will surely degrade the performance of the overall system.  But you think that Quartus will synthesize VHDL only solution?  Best regards, flintstone

[Altera_Forum]

i just did a full compile with a JTAG to MM-Master driving the EPCS Controller

[Altera_Forum]

Thanks, this was really nice :) . 

 So I'll dare to do it.  Best regards, flintstone

[Altera_Forum]

Hello Flintstone, 

 I have a query in relation to an old thread which was initiated by pinkymacy and to which you contributed entitled avalon_mm interface of tse.   I'm having the same issue with waitrequest remaining high when I try to interface to Altera's SDRAM controller. I see from your response that you were able to solve the issue but I didn't fully understand how you did it.   Would you be able to describe in more detail how you solved it or if it's easier, send me a sample of the code you used?  best regards,  John

[Altera_Forum]

Hi johnnie, 

 if I remember correctly there was no problem really, only the name of the signal would lead me in the wrong direction because I thought I have to wait until it goes low before I can start a transaction. Actually it is more like an acknowledge signal, so just apply the signals for a transaction and wait for the waitrequest signal to go low which should happen within a few clock cycles.  HTH flint

[Altera_Forum]

Hi Flint, 

 Thanks for the reply. I thought you were having the same problem as me, but mine is different in that I start the transaction by asserting all the correct signals according to the Avalon spec. The waitrequest goes high initially as I would expect but then it remains high and never deasserts.  I think I'll start a new thread. Thanks anyway,  John