- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello All,
I have a problem with a access to the EPCS . I have a NIOS design with epcs controller. My SW use the altera_avalon_epcs_flash_controller. My HW is a “NiosII Development Board Cyclon (1C20)” and a “NiosII Development Board CyclonII (2C35)”. My design SW is QuartusII 9.0 and 9.1. 1) I load the design with JTAG to the HW I can read an write from/to the EPCS 2) I program this design to EPCS and load from this I can read and write from/to the EPCS 3) I program this design to parallel FLASH and load from this I can NOT read the EPCS. The access to EPCS is not possible. The return value of alt_epcs_flash_init is -19 the return value is -22 if OK. The EPCS is unrealized. This problem is with both Quartus versions and both EVA boards. Why cannot read EPCS if design is load from parallel Flash? Kind regards weibuLink Copied
2 Replies
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
There was an issue when both CFI and EPCS were present and included in SOPC, but that was a couple of years ago Quartus 6
There was a "workaround" as we had used both at the same time, fpga image from cfi and EPCS available for access to store another image + SW + user data- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I have not understood this completely. What I must do with it I can read from the EPCS.
Thanks weibu
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page