Easy design with the VIP suite

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Easy design with the VIP suite

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Hello,

I am learning how to use the VIP suite on a cyclone III C25 board. I put a memory interface (flash, ssram... which is working), a oc_i2c_master, a test generator pattern and a clocked video output. I managed to compile the project but I don't have anything in output.

I chose :

Active pixels : 800

Active lines : 600

Pixel fifo size : 800

H sync : 80

H front porch : 16

H back porch : 160

V sync : 3

V front porch : 2

V back porch : 21

For the test generator pattern, I chose :

Max image width : 800

Max image height : 600

RGB, color plane configuration in parallel, progressive output, color bars

Do someone has an idea ? If you need more details, just ask me.

Thanks,

Myriam

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