Efficient 16-bit std_logic_vector comparator in VHDL

[Kuru]

I'm working on a VHDL project where I need to implement a comparator between two 16-bit std_logic_vector signals, a and b. The goal is to check if a is greater than, less than, or equal to b.

The issue I'm facing is that after synthesis, the comparator uses a significant amount of resources (image below) specifically, it uses 2 CARRY4 blocks and too much LUTs. My professor, who assigned this task, explicitly stated that I must not convert a and b to integer, unsigned, or any other numeric type. They must be compared as std_logic_vector.

Is there a way to implement a more resource-efficient comparator under these constraints? Any ideas or patterns to reduce the number of LUTs or avoid the use of carry chains would be appreciated.

Here is the code :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity comparator is
    Port (
        clk, rst : in std_logic;
        a, b     : in std_logic_vector (15 downto 0);
        max, min : out std_logic_vector (15 downto 0)
    );
end comparator;

architecture Behavioral of comparator is

signal max_int, min_int : std_logic_vector (15 downto 0);
begin

process (clk)
begin   
    if (rst = '1') then
    
        min_int <= (others => '0');
        max_int <= (others => '0');
       
    elsif (rising_edge(clk)) then
    
        if (a <= b) then
            min_int <= a;
            max_int <= b;
        else
            min_int <= b;
            max_int <= a;
        end if;
        
    end if;

Thanks in advance!

[FvM]

Using different numerical types has no effect on resource consumption, arithmetic operation is essentially the same.

Using carry chain is appropriate for fast comparator, Quartus selects it automatically as default implementation.

Most LUT are used for 32 mux output bits and have nothing to do with comparator function as such.

[Kuru]

So, are there no alternatives? Is this the best solution?
Do you think I could write the VHDL code in a way that uses even fewer resources?

[FvM]

Forgot to mention, to perform numeric operations with std_logic_vector, you need to add VHDL2008 numeric_unsigned or numeric_signed library. Or non-standard Synopsis library before VHDL2008.

[RichardTanSY_Altera]

.

[RichardTanSY_Altera]

Altera provides the LPM_COMPARE IP core, which can be used for more efficient logic synthesis and device implementation compared to writing your own comparator functions. This IP core is customizable to meet specific design requirements.

Here’s the official documentation for reference:

https://www.intel.com/content/www/us/en/docs/programmable/683490/25-1/lpm-compare-comparator.html

I understand your professor may require you to implement the logic manually, but I just wanted to point out that using Altera IP cores can significantly speed up design development.

Regards,

Richard Tan

[RichardTanSY_Altera]

We noticed that we haven't received a response from you regarding the latest previous question/reply/answer, and will now transitioning your inquiry to our community support. We apologize for any inconvenience this may cause and we appreciate your understanding.

If you have any further questions or concerns, please don't hesitate to reach out. Please login to https://supporttickets.intel.com/s/?language=en_US, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

The community users will be able to help you on your follow-up questions.

Thank you for reaching out to us!

Best Regards,

Richard Tan