Embedding SDC constraints in Verilog HDL source code

Altera_Forum · ‎07-02-2010

Is it possible to embed SDC constraints ourself using verilog HDL source code? If yes, can someone tell me how to do?

Altera_Forum · ‎07-02-2010

I believe you use a Verilog attribute statement ...


(* ALTERA_ATTRIBUTE = “-name SDC_STATEMENT set_multicycle_path -end -setup -from  -to [get_registers *|REG2)

Jake

Altera_Forum · ‎07-02-2010

Thanks for your quick reply....This is exactly what I want....

Altera_Forum · ‎07-19-2011

is it somehow possible to attach a timing contraint to a reg definition?

I've found this:

reg    q2;
// Equivalent to set_instance_assignment -name CUT ON -from q1 -to q2
(* altera_attribute = "-name CUT ON -to q2" *) reg q1;

on:

but I believe that's only working with classic timing analyser. is there something an equivalent for timequest??