Emulation AVST Mailbox IP in Agilex

[liny]

Hi,

When I use AVST Mailbox IP to read CHIP ID and temperature, I need to design a program that can read the data. When I want to simulate Mailbox IP first, after normal reset in quesa, the output signal is always wrong. The user guide of Mailbox IP mentions that simulation can be supported, but in fact I have not succeeded

The clock is 50M, and the high level of the reset signal is 5us,But after the reset, the ready signal output by AVST Mailbox IP is always 'z'

[ShengN_Intel · Accepted solution]

Hi,

Check out this link https://www.intel.com/content/www/us/en/docs/programmable/683510/22-4-1-0-2/device-family-support.html, there's a note there:

Note: You cannot simulate the Mailbox Client with Avalon® Streaming Interface Intel® FPGA IP because the IP receives the responses from the SDM. To validate this IP, Intel recommends that you perform hardware evaluation.

Example design link:

https://www.intel.com/content/www/us/en/design-example/763981/agilex-chip-id-reading-using-avst-mailbox-ip.html

Probably have to use on-chip debug tool signal tap to view the simulation check image below:

Thanks,

Best regards,

Sheng

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.