Error (10002): Can't open VHDL or Verilog HDL file
I am new to Altera/Quartus, but do have FPGA design experience. I am trying to complete a lab, but when I try to compile my Qsys generated design, I get:
Error (10002): Can't open VHDL or Verilog HDL file "C:/project_dir/" It seems that the error is caused by a missing file, but why is listing a directory? All of my design files are found correctly in the "C:/project_dir/synthesis/" directory. I am not sure how to debug what/where this error is occurring. Any help in how to debug this would be great.