Error 10200

Altera_Forum · ‎01-06-2011

Hi Everyone,

When trying to synthesize the following code I get the error:

Error (10200): Verilog HDL Conditional Statement error at prog_counter.v(62): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct

The code is from the book Verilog Coding for Logic Synthesis by Weng Lee (Ch. 6)

What generally causes this type of error?

Here is the code with the problem line indicated

always @(ceb or write or reset or load or data_in)
begin
	if (~ceb & write & ~load & ~reset & ~flag_counter)
		control_word_register = data_in ;
	else if (~ceb & ~write & load & ~reset & ~flag_counter)
		latch_counter = data_in;
	else if (ceb & ~reset)
		begin
			//reset the control word counter
			control_word_register = 0;
			//reset the latch
			latch_counter = 0;
		end
	else if (disable_CWR)
			control_word_register = 0;
end
	
	//to counter for counter
	
always @(posedge clk or posedge reset or posedge trigger)
	begin
		if(reset)
		begin
			disable_CWR <= 0;
			flag_counter <= 0;
			counter <= 0;
			flag_half_counter<=0;
		end
		else
		begin
       >>Error <<  if(control_word_register) //counter is enabled << *****Error 10200 Here******
			begin
				if(control_word_register == 2'b00)	//this if for one shot mode
				begin
					if(~flag_counter)
						begin
						counter <= latch_counter;
						flag_counter <=1;
						end
					else
						begin
						if(counter == 8'hff)
							begin
							//to stop counter for one shot mode
							disable_CWR <= 1;
							flag_counter <=0;
							end
						else
							counter <= counter + 1;
						end
				end
				else if (control_word_register == 2'b01) //waveform generator mode
				begin
					if(~flag_counter)
						begin
							counter <= latch_counter;
							flag_counter <= 1;
						end
					else
						begin
							if(counter == 8'hff)
								flag_counter <= 0;
							counter <= counter + 1;
						end
				end
				else if(control_word_register == 2'b10) //this if for the 5-% duty cycle waveform generator
				begin
					if(~flag_counter)
					begin
						counter <= latch_counter;
						flag_counter <= 1;
					end
					else
					 begin
						  if (counter == {1'b0,latch_counter})
							 begin
								  flag_half_counter <= ~flag_half_counter;
								  counter <= counter - 1;
							 end
						  else
							 if (counter == 0)
								flag_counter <= 0;
							 else
								counter <= counter - 1;
					 end
				end
			else if(control_word_register == 2'b11)//this is for triggered pulse generator mode
			  begin
			    if(~flag_counter)
			      begin
					//If we aren't currently sending out a pulse, then keep the counter loaded and ready
					//this also resets the counter after a successful pulse is generated so that we will be ready for the next trigger
					counter <= latch_counter; 
			        if(trigger)
			           flag_counter <= 1;
			        else
			           flag_counter <= 0;
			      end
			    else
			      if(counter == 8'hff)
			        begin //stop counter for triggered pulse mode
			         flag_counter <= 0;
			        end
			       else
			         counter <= counter + 1;
			   end
			  
		end
	end
end

The Problem appears in the second always block on the line

if(control_word_register) //counter is enabled << *****Error 10200 Here******

Any input on this is really appreciated...

Altera_Forum · ‎01-06-2011

Figured it out, it was the fact that the second always block was sensitive to the trigger. I removed it from the event list and just sync the trigger to the clock before it reaches this module.

Altera_Forum · ‎05-23-2017

Thank you, I had the same problem. Worked for me too.