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LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
-- Entity Declaration
ENTITY add_sub IS
PORT
(
A,B : IN STD_LOGIC_VECTOR(3 downto 0);
SEL : IN STD_LOGIC;
S : OUT STD_LOGIC_VECTOR(3 downto 0);
CoBo : OUT STD_LOGIC
);
END add_sub;
-- Architecture Body
ARCHITECTURE add_sub_architecture OF add_sub IS
--signals goes here
signal s1,s2 : STD_LOGIC_VECTOR(3 downto 0);
signal c1,c2 : STD_LOGIC;
BEGIN
add: process(A, B)
--variables goes here
variable p: std_logic_vector (4 downto 0);
begin
--describtion goes here
p := ('0'& A) + ('0'& B);
s1 <= p(3 downto 0);
c1 <= p(4);
end process;
--next processes 2
sub : process (B, A)
--variables goes here
variable n: std_logic_vector (4 downto 0);
begin
--describtion goes here
n := ('0'& A) - ('0'& B);
s2 <= n(3 downto 0 );
c2 <= n(4);
end process;
--next processes 3
pick: process (s1, s2, c1, c2, sel)
--variables goes here
begin
--describtion goes here
if sel ='0' then
add <= s1;
CoBo <= c1;
else
sub <= s2;
CoBo <= c2;
end if;
end process;
END add_sub_architecture;
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Hi,
Line add <= s1;
add is variable right, check the assignment to a variable.
must be like add := s1;
Please note that, I have not checked the complete code.
Let me know if this has helped resolve the issue you are facing or if you need any further assistance.
Best Regards,
Anand
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add and sub are process labels and are illegal assignments. If you want to call them as functions, you will have to declare both add and sub as functions and not processes.
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oh ok, got it ,thanks.

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