I'm trying to implement a DDR3 based frame buffer using a Stratix IV FPGA. I'm using the Tr4 FPGA development kit.
When I compile my design, I'm getting the following error message.
"
Error (15852): Output port "O" of PSEUDO_DIFF_OUT primitive "FB_1:u0|FB_1_mem_if_ddr3_emif_0:mem_if_ddr3_emif_0|FB_1_mem_if_ddr3_emif_0_p0:p0|FB_1_mem_if_ddr3_emif_0_p0_memphy:umemphy|FB_1_mem_if_ddr3_emif_0_p0_new_io_pads:uio_pads|FB_1_mem_if_ddr3_emif_0_p0_addr_cmd_pads:uaddr_cmd_pads|FB_1_mem_if_ddr3_emif_0_p0_clock_pair_generator:clock_gen[0].uclk_generator|pseudo_diffa_0" must drive only one OBUF primitive on the I port and cannot drive anything else
"
I saw some older threads with similar problems. However, I did run the tcl scripts and changed the differential pin assignments to single ended ones(as suggested in an earlier thread on a similar issue). However, the error does not seem to go away.
