Error 169182 with Cyclone 10 LP

[AlexBarry]

I am compiling a design for the Cylcone 10 LP (10CL025YE144I7G).  We use using active serial configuration mode.  Currently, we have a 3.3V LVCMOS output signal on pin 11.  When I added the serial flash loader, I started getting a 169182 error ("Cannot place I/O pin SLF1:xxxx in pin location 12 -- possible switch coupling..."

The knowledge base article I found on this (https://www.intel.com/content/www/us/en/support/programmable/articles/000079651.html) indicates this is a restriction for some Cyclone III and IV parts, but doesn't mention Cyclone 10 LP.

Can I correct this without moving the output signal pin away from pin 11?

[AqidAyman_Intel]

Hi,

May I know if you have tried to change the I/O standard of that pin to 2.5V?

did the error message still observed?

If yes, then it is likely the same rule happened for the device as well which is to minimizes noise coupling from neighboring I/Os to the DCLK pin.

Regards,

Aqid

[AlexBarry]

We have not tried that, since all of the devices attached to the FPGA will require 3.3V IO.  The configuration device is also 3.3V. We do have the option of moving this signal to another pin.

[FvM · Accepted solution]

Hi,
why do you need SFL integrated with application code. Standard solution would be default SFL image loaded by programmer, it doesn't conflict with any application pin assignments. 

[AqidAyman_Intel]

Hi,

Have you tried the solution suggested by @FvM?

[AlexBarry]

That solution builds fine. We were hoping to have an in-system update capability that would not pause application functionality, but that's just a desired feature, not a hard requirement.

[AqidAyman_Intel]

Hi,

Thank you for your confirmation. I really appreciate your suggestion. I can help to recommend this for future enhancements.

With that being said, can we close this thread? If no, please let me know if you need more support. I will be happy to help you more.

Regards,

Aqid