Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20686 Discussions

Error 170084 ADC & PLL

Altera_Forum
Honored Contributor II
2,876 Views

Given: 

Quartus 14.1.1 build190 

BeMicro Max 10 

10M08DAF484 

System clock on N14 

Error (170084): Can't route signal "ADC06:inst|ADC06_altpll_0:altpll_0|ADC06_altpll_0_altpll_5q22:sd1|wire_pll7_clk[0]" to atom "ADC06:inst|ADC06_ADC:adc|altera_modular_adc_control:control_internal|fiftyfivenm_adcblock_top_wrapper:adc_inst|fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|primitive_instance" 

 

ADC.qip is the only file in the project and it consists of Qsys IP "Altera Modular ADC core, Avalon ALTPLL and JTAG to Avalon Master Bridge. 

 

I am having trouble compiling a the project using system clock on N14. If I compile the project on Clock pin N9 then compilation will complete without errors. 

 

What am I doing wrong? 

 

Thank you in advance. 

Mike
0 Kudos
12 Replies
Altera_Forum
Honored Contributor II
1,490 Views

I found that if I inserted another ALTPLL between the N14 clock pin and the Qsys ADC symbol the project will compile. 

 

Why are two ALTPLL's required? 

 

Mike
0 Kudos
Altera_Forum
Honored Contributor II
1,490 Views

I think that a PLL can have only one clock input. You have two clocks, thus you need two PLLs? It might also work with two QSYS clk input blocks.

0 Kudos
Altera_Forum
Honored Contributor II
1,490 Views

The Qsys pictures below better describes the problem. If I attach the system clock pin to N14 I must add a second altpll (altpll_1) or the compiler will fail in fitter. If I attach the system clock pin to N9 then I can use a single altpll (altpll_0) and compile without errors. 

 

I am wondering why fitter cannot connect to N14 with a single altpll. 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=10213 2 altpll 

https://www.alteraforum.com/forum/attachment.php?attachmentid=10214 1 altpll 

 

Mike
0 Kudos
Altera_Forum
Honored Contributor II
1,490 Views

I found it. Bummer! 

 

From the Max 10 ADC data sheet. 

"Depending on the device package, the MAX 10 devices support one or two PLLs—PLL1 only, or PLL1 and 

PLL3." 

 

The BeMicro Max 10 Sys Clk is on pin N14 or PLL2. 

 

Mike
0 Kudos
Altera_Forum
Honored Contributor II
1,490 Views

 

--- Quote Start ---  

I found it. Bummer! 

 

From the Max 10 ADC data sheet. 

"Depending on the device package, the MAX 10 devices support one or two PLLs—PLL1 only, or PLL1 and 

PLL3." 

 

The BeMicro Max 10 Sys Clk is on pin N14 or PLL2. 

 

Mike 

--- Quote End ---  

 

And what about QSYS ADC tool, does it work with all of it? In my case - no. :cry:
0 Kudos
Altera_Forum
Honored Contributor II
1,490 Views

It turns out you can use the Assignments Editor to specify a location for a given instance of the PLL. On a new (blank) line, select "location" In the Category column. Use the Node Finder in the "To" column to find the instance. Then in the Value column, select the element type as PLL, which in my case gives two choices: PLL_1 and PLL_2. I found PLL_1 is the useful one. 

 

 

By the way, the very next sentence following "Depending on the device package, the MAX 10 devices support one or two PLLs—PLL1 only, or PLL1 and PLL3." is "For devices that support two PLLs, you can select which PLL to connect to the ADC." which seems to be incorrect.
0 Kudos
Altera_Forum
Honored Contributor II
1,490 Views

hi i have the same error-code 

 

coud you take a screenshot of the pinn-assignment ?
0 Kudos
Altera_Forum
Honored Contributor II
1,490 Views

Sure, see attachment. Haha assuming I can get this pokey web site to work

0 Kudos
Altera_Forum
Honored Contributor II
1,490 Views

I wasted too much time on this board. I ended up making my own Max10 prototype board with 25Mhz clock, JTAG, 8Mb SDRAM, (2)4ch opamps and .1" headers. 

 

We tend to look for all the bells and whistles when we first start out, but less is more. It can be very frustrating going back and forth through their schematics to find out which IO is not being used by their added peripherals. Several of these pins can be shared but you end up looking through all of the data sheets to find which ones. 

 

The Altera EK-10M08E144ES/P is a nice simple evaluation board. I would have purchased this board if it had SDRAM.
0 Kudos
Altera_Forum
Honored Contributor II
1,490 Views

Hi Kikell7, are you using E144 part on your own design? 

I am stuck at my design still refuse to work, I think I can buy EK10m08, but I am using SC part and Ek moount an SA. 

Pin variation across model on E144 series is another trouble, so seems like 5 series exists, 02, 08sa-25sa, 08sc-25sc, 40-50SA, 40-50SC. 

Regards
0 Kudos
Altera_Forum
Honored Contributor II
1,490 Views

What doesn't work? 

Mike
0 Kudos
Altera_Forum
Honored Contributor II
1,490 Views

Hi Mikell, it refuse to program after first time. 

Here is detail of what happened,  

http://www.alteraforum.com/forum/showthread.php?t=54757 

 

today I try'd to load a simple counter dividing 50MHz sys input clock then driving some pin to 0 and with 1MHz, 500 & 250KHz toggle. Pin remain as it where open. SOF say success but doesn't work, Flash accept just erase and examine. 

Thank in advance. 

Roberto
0 Kudos
Reply