Error Found, when I use LogicLock to constraint my design!

[Altera_Forum]

HI! Everybody! 

 The FPGA is EP1C3T144C8, and the design need about 1300 cells.   when I try to use LogicLock to constraint my design, I failed. and the following is the error message:   Error: Fitter requires that more entities of type logic cell be placed in a region than are available in the region  Error: Region "lower-left" corner: X4_Y4; Region "upper-right" corner: X18_Y11  Info: Region constraint came from a User-Defined LogicLock Region  Error: Region can accept 920 entities of type logic cell, but the Fitter needs to place 2156 of them in this region   So ,In this sitution, I　wonder if there is a document or a way to tell us to calculate the accurate value of X?_Y? and Width or Hight, I need your help! thankyou

[Altera_Forum]

take a look at the architecture: 

 http://www.altera.com/literature/hb/cyc/cyc_c51002.pdf  the Cyclone lab contains 10 LEs. in Chip Planner, you should be able to identify the LABs (vs the M4K, etc), and draw a region containing enough for your design  why are you using LogicLock?

[Altera_Forum]

HI! thepancake, 

 the design above is only a submodule for display , so I want to use LogicLock to constraint my every module.   I have read the document you suggested before, however, the question is still exist,the design needs 1196 LEs , So I set the Width to 15, Hight to 12 , (15*12*10=1800>1196),the Origin is X2_Y2, and I'm so sure that there will be no errors , but when I compile the design,the error message is:   Error: Fitter requires that more entities of type logic cell be placed in a region than are available in the region. Error: Region "lower-left" corner: X2_Y2; Region "upper-right" corner: X16_Y13 Error: Region can accept 1380 entities of type logic cell, but the Fitter needs to place 2220 of them in this region   Fortunately, when I set the Width to 25, Hight to 12(25*12*10=3000),the Origin is X2_Y2,the compilation is OK,.   I wonder when I set the Width to 15, Hight to 12(15*12*10=1800>1196),the Origin is X2_Y2, Region only can accept 1380 entities of type logic cell ! why ?   In addition,I can't understand why the Fitter needs to place 2220 of them in this region correctly, I need your help!

[Altera_Forum]

Anyone knows ? I'm looking forward to your reply!

[Altera_Forum]

did you consider that not every column is a logic LAB in your equation? you may be counting a column of block RAM as LEs

[Altera_Forum]

Yes. I have considered before, The FPGA also contain many other dedicated module, Thankyou,thepancake.