Error: HSSI PMA TX Buffer node after signaltap

[EDICHARA]

Hello World, I have a project that compiles without errors, and the project is work. But when I add certain signals (the output signals of the transmitter created with the "Arria V Transceiver Native v15.0" megafunction to the SignalTap, errors appear during compilation. How to solve this problem? When you remove the SignalTap from the project, compilation occurs without errors. Thank you.

Error: HSSI PMA TX Buffer node 'CPU_CPS_QSYS:CPU_CPS_QSYS_inst|CPS_IOCC:cps_iocc|ArriaV_NativePHY_8:ArriaV_NativePHY_8_inst|native_phy_tx:native_phy_tx_inst|altera_xcvr_native_av:native_phy_tx_inst|av_xcvr_native:gen_native_inst.av_xcvr_native_insts[0].gen_bonded_group_native.av_xcvr_native_inst|av_pma:inst_av_pma|av_tx_pma:av_tx_pma|av_tx_pma_ch:tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_pma_buf.tx_pma_buf'

is not properly connected on the 'DATAOUT' port. It must be connected to one of the valid ports listed below.
Info: Can be connected to I port of arriav_io_obuf WYSIWYG

[Deshi_Intel]

Hi,

You can't use signal_tap to probe on hard circuit block like TX PMA buffer. That's why you can error message.

Signal_tap can only be used to probe on interface bus that connect to FPGA core logic only.

• For Eg : tx_parrallel_data bus or rx_parrallel_data from NativePHY IP

Thanks.

Regards,

dlim

[EDICHARA]

Thanks.