Error: Input port "DPRIOCLK" must be driven by the same source

[Altera_Forum]

Hi, 

I facing the problem with the GXB Reference clock routing. My design insatnces are PCIe, HD-SDI Receiver and SD-SDI Receiver. i connected the GXB calibration clock output of PCIe to HD-SD IPs GXB cal clock. the HD-SDI[CH# 0] reference clock connected to FPGA dedicated transceiver clock pins [AA29,AA30{BANK QL2}], Arria ii gx EP2AGX125EF]. and SD-SDI[CH# 6] oversampling clock connected from the ALTPLL which intern connected from bank 8A, F17 pin[LVCMOS33].    Fitter tool throwing fallowing error; --========================================================= Error: Can't assign I/O pad "i_HD_SDI_Rx2" to PIN_AA33 because this causes failure in the placement of the other atoms in its associated channel  Error: Quartus II software cannot combine the following GXB Central control unit(s) due to inconsistent parameters and/or input connections    Error: Input port "DPRIOCLK" must be driven by the same source   Info: Atom "hd_sdi_interface:hd_sdi_interface_inst|hd_sdi_rx0:hd_sdi_rx0_inst|sdi_megacore_top:sdi_megacore_top_inst|sdi_txrx_port:sdi_txrx_port_gen[0].u_txrx_port|rc_s4gxb_rx:gen_rx_alt4gxb.u_gxb|alt4gxb:alt4gxb_component|alt4gxb_2ca6:auto_generated|cent_unit0" is driven by source "i_HD_Ref_Clk_74_25M"   Info: Atom "hd_sdi_interface:hd_sdi_interface_inst|sd_sdi:sd_sdi_rx1_inst|sdi_megacore_top:sdi_megacore_top_inst|sdi_txrx_port:sdi_txrx_port_gen[0].u_txrx_port|rc_s4gxb_rx:gen_rx_alt4gxb.u_gxb|alt4gxb:alt4gxb_component|alt4gxb_4aa6:auto_generated|cent_unit0" is driven by source "pll3:pll3_inst|altpll:altpll_component|pll3_altpll:auto_generated|wire_pll1_clk[0]" --======================================================== I replaced the single clock source then there is no error. But its need me to rout the reference clock from the different clock sources.   quick solution is appreciated. Thanks..

[Altera_Forum]

Hi, 

I have corrected the foolish thing what i did. the tool is clearly define the issue but i cant not able to catch due to tool gives an error relating to internal signals of mega core which i was not known.  The DPRIOCLK is the The dynamic partial reconfigurable I/O {sdi_reconfig_clk} which should be driven by the same clock source of all ip channels.   Thanks.